LPC2387 datasheet(24/66 Pages) NXP

24 / 66 page

LPC2387

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Product data sheet

Rev. 5.1 — 16 October 2013

24 of 66

NXP Semiconductors

LPC2387

Single-chip 16-bit/32-bit MCU

7.17 SD/MMC card interface

The Secure Digital and Multimedia Card Interface (MCI) allows access to external SD

memory cards. The SD card interface conforms to the SD Multimedia Card Specification

Version 2.11.

7.17.1 Features

• The MCI provides all functions specific to the SD/MMC memory card. These include

the clock generation unit, power management control, and command and data

transfer.

• Conforms to Multimedia Card Specification v2.11.

• Conforms to Secure Digital Memory Card Physical Layer Specification, v0.96.

• Can be used as a multimedia card bus or a secure digital memory card bus host. The

SD/MMC can be connected to several multimedia cards or a single secure digital

memory card.

• DMA supported through the GPDMA controller.

7.18 I2C-bus serial I/O controllers

The LPC2387 contains three I2C-bus controllers.

The I2C-bus is bidirectional, for inter-IC control using only two wires: a Serial CLock line

(SCL), and a Serial DAta line (SDA). Each device is recognized by a unique address and

can operate as either a receiver-only device (e.g., an LCD driver) or a transmitter with the

capability to both receive and send information (such as memory). Transmitters and/or

receivers can operate in either master or slave mode, depending on whether the chip has

to initiate a data transfer or is only addressed. The I2C is a multi-master bus, it can be

controlled by more than one bus master connected to it.

The I2C-bus implemented in LPC2387 supports bit rates up to 400 kbit/s (Fast I2C-bus).

7.18.1 Features

• I2C0 is a standard I2C compliant bus interface with open-drain pins.

• I2C1 and I2C2 use standard I/O pins and do not support powering off of individual

devices connected to the same bus lines.

• Easy to configure as master, slave, or master/slave.

• Programmable clocks allow versatile rate control.

• Bidirectional data transfer between masters and slaves.

• Multi-master bus (no central master).

• Arbitration between simultaneously transmitting masters without corruption of serial

data on the bus.

• Serial clock synchronization allows devices with different bit rates to communicate via

one serial bus.

• Serial clock synchronization can be used as a handshake mechanism to suspend and

resume serial transfer.

• The I2C-bus can be used for test and diagnostic purposes.

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