PCM1820 datasheet(8/44 Pages) TI

8 / 44 page

at TA = 25°C, IOVDD = 3.3 V or 1.8 V and 20-pF load on all outputs (unless otherwise noted); see Figure 7-2 for timing

diagram

MIN

NOM

MAX

UNIT

tH(BCLK)

BCLK high pulse duration (1)

tL(BCLK)

BCLK low pulse duration (1)

tSU(FSYNC)

FSYNC setup time

tHLD(FSYNC)

FSYNC hold time

tr(BCLK)

BCLK rise time

10% - 90% rise time(2)

tf(BCLK)

BCLK fall time

90% - 10% fall time(2)

(1)

The BCLK minimum high or low pulse duration must be higher than 25 ns (to meet the timing specifications), if the SDOUT data line is

latched on the opposite BCLK edge polarity than the edge used by the device to transmit SDOUT data.

(2)

BCLK maximum rise and fall time can be relaxed to 13ns if BCLK frequency used in the system is below 20MHz. This can cause noise

increase due to higher clock jitter.

7.6 Switching Characteristics: TDM, I2S or LJ Interface

at TA = 25°C, IOVDD = 3.3 V or 1.8 V and 20-pF load on all outputs (unless otherwise noted); see Figure 7-2 for timing

diagram

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

td(SDOUT-BCLK)

BCLK to SDOUT delay

50% of BCLK to 50% of SDOUT

td(SDOUT-FSYNC)

FSYNC to SDOUT delay in TDM

or LJ mode (for MSB data with

TX_OFFSET = 0)

50% of FSYNC to 50% of

SDOUT

f(BCLK)

BCLK output clock frequency:

master mode (1)

24.576

MHz

tH(BCLK)

BCLK high pulse duration: master

mode

tL(BCLK)

BCLK low pulse duration: master

mode

td(FSYNC)

BCLK to FSYNC delay: master

mode

50% of BCLK to 50% of FSYNC

tr(BCLK)

BCLK rise time: master mode

10% - 90% rise time

tf(BCLK)

BCLK fall time: master mode

90% - 10% fall time

(1)

The BCLK output clock frequency must be lower than 18.5 MHz (to meet the timing specifications), if the SDOUT data line is latched

on the opposite BCLK edge polarity than the edge used by the device to transmit SDOUT data.

PCM1820-Q1, PCM1821-Q1

SBASAH4 – APRIL 2022

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