PCM1820 datasheet(13/44 Pages) TI

13 / 44 page

8 Detailed Description

8.1 Overview

The PCM182(0/1)-Q1 is a high-performance, low-power, stereo-channel, audio analog-to-digital converter (ADC)

with flexible audio interface control options. This device is intended for applications in automotive head units,

display control unit, Active Noise Cancellation and Acoustic Echo Cancellation applications. The high dynamic

range of the device enables far-field audio recording with high fidelity. This device integrates a host of features

that reduces cost, board space, and power consumption in space-constrained applications. The device features

are controlled through hardware by pulling pins high or low with resistors or a controller general-purpose inut/

output (GPIO). The PCM182(0/1)-Q1 also supports a power-down and reset function by means of halting the

system clock.

The PCM182(0/1)-Q1 consists of the following blocks and features:

• Stereo-channel, multibit, high-performance delta-sigma (ΔΣ) ADC

• Differential audio inputs with a 2-VRMS full-scale signal

• Hardware pin control operation to select the device features

• Audio bus serial interface master or slave select option

• Audio bus serial interface format select option

• Slave mode supports the audio bus serial interface up to 192 kHz sampling

• Slave mode supports a dynamic range enhancer (DRE) with 123-dB dynamic range for the PCM1820-Q1

• Slave mode supports decimation filters with linear-phase or low-latency filter selection

• Master mode operation supported using a system clock of 256 × fS or 512 × fS

• Power-down function by means of halting the audio clocks

• Integrated high-pass filter (HPF) that removes the DC component of the input signal

• Integrated low-jitter phase-locked loop (PLL) supporting a wide range of system clocks

• Integrated digital and analog voltage regulators to support single-supply, 3.3-V operation

8.2 Functional Block Diagram

ADC

Channel-1

Digital

Decimation

Filters

with High Pass

Filter (HPF)

Audio Serial

Interface

(TDM, I2S)

BCLK

FSYNC

SDOUT

IN1M

IN1P

IN2M

IN2P

ADC

Channel-2

Regulators, Current Bias

and Voltage Reference

Clock and Timing

Controller with

Integrated PLL

www.ti.com

PCM1820-Q1, PCM1821-Q1

SBASAH4 – APRIL 2022

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Product Folder Links: PCM1820-Q1 PCM1821-Q1

PCM1820 Datasheet(PDF) 13 Page - Texas Instruments

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