| Electronic Components Datasheet Search |
|
ATAR080 Datasheet(PDF) 8 Page - ATMEL Corporation |
|
|
|||||||||||||||||||||||||||||
ATAR080 Datasheet(HTML) 8 Page - ATMEL Corporation |
|
8 / 68 page ![]() 8 ATAR080 4675D–4BMCU–12/04 Figure 8. Interrupt Handling Interrupt Processing In order to be able to process eight interrupt levels, the MARC4 contains an interrupt controller with two 8-bit wide “interrupt pending” and “interrupt active” registers. The interrupt controller samples all interrupt requests during every non-I/O instruction cycle and latches these in the interrupt pending register. If no higher priority interrupt is present in the interrupt active register, it signals the CPU to interrupt the current pro- gram execution. If the interrupt enable bit is set, the processor enters an interrupt acknowledge cycle. During this cycle a short call (SCALL) instruction to the service rou- tine is executed and the current PC is saved on the return stack. An interrupt service routine is completed with the RTI instruction. This instruction resets the corresponding bits in the interrupt pending/active register and fetches the return address from the return stack to the program counter. When the interrupt enable flag is reset (triggering of interrupt routines are disabled), the execution of new interrupt service routines is inhib- ited but not the logging of the interrupt requests in the interrupt pending register. The execution of the interrupt is delayed until the interrupt enable flag is set again. Note that interrupts are only lost if an interrupt request occurs while the corresponding bit in the pending register is still set (i.e., the interrupt service routine is not yet finished). Interrupt Latency The interrupt latency is the time from the occurrence of the interrupt to the interrupt ser- vice routine being activated. This is extremely short (taking between 3 to 5 machine cycles depending on the state of the core). 7 6 5 4 3 2 1 0 INT5 active INT7 active INT2 pending SWI0 INT2 active INT0 pending INT0 active INT2 RTI RTI INT5 INT3 active INT3 RTI RTI RTI INT7 Time Main/ Autosleep Main/ Autosleep RTI |
|
Link URL |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link to Datasheet | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |