ATAR080 datasheet(47/68 Pages) ATMEL

47 / 68 page

ATAR080

4675D–4BMCU–12/04

Figure 50. MCL Bus Protocol 2

SSI Interrupt

The SSI interrupt INT3 can be generated either by an SSI buffer register status (i.e.,

transmit buffer empty or receive buffer full) at the end of an SSI data telegram or on the

falling edge of the SC/SD pins on Port 4 (see P4CR). SSI interrupt selection is per-

formed by the Interrupt FunctioN control bit (IFN). The SSI interrupt is usually used to

synchronize the software control of the SSI and inform the controller of the present SSI

status. Port 4 interrupts can be used together with the SSI or, if the SSI itself is not

required, as additional external interrupt sources. In either case this interrupt is capable

of waking the controller out of sleep mode.

To enable and select the SSI relevant interrupts use the SSI interrupt mask (SIM) and

the Interrupt Function (IFN) while Port 4 interrupts are enabled by setting appropriate

control bits in P4CR register.

Modulation

If the shift register is used together with Timer 2 for modulation purposes, the 8-bit syn-

chronous mode must be used. In this case, the unused Port 4 pins can be used as

conventional bi-directional ports.

The modulation stage, if enabled, operates as soon as the SSI is activated (SIR = 0) and

ceases when deactivated (SIR = 1).

Due to the byte-orientated data control, the SSI (when running normally) generates

serial bit-streams which are submultiples of 8 bits. However, an SSI output masking

(OMSK) function permits the generation of bit-streams of any length. The OMSK signal

is derived indirectly from the 4-bit prescaler of the Timer 2 and masks out a programma-

ble number of unrequired trailing data bits during the shifting out of the final data word in

the bit stream. The number of non-masked data bits is defined by the value pre-pro-

grammed in the prescaler compare register. To use output masking, the modulator stop

mode bit (MSM) must be set to '0' before programming the final data word into the SSI

transmit buffer. This in turn, enables shift clocks to the prescaler when this final word is

shifted out. On reaching the compare value, the prescaler triggers the OMSK signal and

all following data bits are blanked.

Start

1st Bit

8th Bit

ACK

Stop

ATAR080 Datasheet(PDF) 47 Page - ATMEL Corporation