ATAR080 datasheet(18/68 Pages) ATMEL

18 / 68 page

ATAR080

4675D–4BMCU–12/04

Clock Management Register

(CM)

System configuration Register

(SC)

Note:

If the bit CCS = 0 in the CM-register the RC-oscillator 1 always stops.

Auxiliary register address:

'3'hex

Bit 3Bit 2Bit 1Bit 0

NSTOP

CCS

CSS1

CSS0

Reset value: 1111b

NSTOP

Not STOP peripheral clock

NSTOP = 0, stops the peripheral clock while the core is in SLEEP mode

NSTOP = 1, enables the peripheral clock while the core is in SLEEP mode

CCS

Core Clock Select

CCS = 1, the internal RC-oscillator 1 generates SYSCL

CCS = 0, the 4-Mhz crystal oscillator, the 32-kHz crystal oscillator, an external

clock source or the RC-oscillator 2 with the external resistor at OSC1

generates SYSCL dependent on the setting of OS0 and OS1 in the

system configuration register

CSS1

Core Speed Select 1

CSS0

Core Speed Select 0

Table 6. Core Speed Select

CSS1

CSS0

Divider

Note

Reset value

Primary register address: ’3’hex

Bit 3Bit 2Bit 1Bit 0

SC: write

BOT

–

OS1

OS0

Reset value: 1x11b

BOT

Brown-Out Threshold

BOT = 1, low brown-out voltage threshold (1.65 V)

BOT = 0, high brown-out voltage threshold (1.95 V)

OS1

Oscillator Select 1

OS0

Oscillator Select 0

Table 7. Oscillator Select

Mode

OS1

OS0

Input for SUBCL

Selected Oscillators

in/16

RC-oscillator 1 and external input clock

in/16

RC-oscillator 1 and RC-oscillator 2

in/16

RC-oscillator 1 and 4-MHz crystal oscillator

32 kHz

RC-oscillator 1 and 32-kHz crystal oscillator

ATAR080 Datasheet(PDF) 18 Page - ATMEL Corporation

ATAR080 Datasheet(HTML) 18 Page - ATMEL Corporation

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