ATAR080 datasheet(30/68 Pages) ATMEL

30 / 68 page

ATAR080

4675D–4BMCU–12/04

Watchdog Control Register

(WDC)

Bit 3 = MSB, Bit 0 = LSB

Both these bits control the time interval for the watchdog reset

Note:

in: input clock period = 1/Cin (see Figure 14 on page 14)

Timer 2

Timer 2 is an 8-/12-bit timer used for:

•

Interrupt, square-wave, pulse and duty cycle generation

•

Baud-rate generation for the internal shift register

•

Manchester and Bi-phase modulation together with the SSI

•

Carrier frequency generation and modulation together with the SSI

Timer 2 can be used as an interval timer for interrupt generation, as signal generator or

as baud-rate generator and modulator for the serial interface. It consists of a 4-bit and

an 8-bit up counter stage which both have compare registers. The 4-bit counter stages

of Timer 2 are cascadable as a 12-bit timer or as an 8-bit timer with a 4-bit prescaler.

The timer can also be configured as an 8-bit timer and a separate 4-bit prescaler.

The Timer 2 input can be supplied via the system clock, the external input clock (T2I),

the Timer 1 output clock or the shift clock of the serial interface. The external input clock

T2I is not synchronized with SYSCL. Therefore, it is possible to use Timer 2 with a

higher clock speed than SYSCL. Furthermore, with that input clock the Timer 2 operates

in the power-down mode SLEEP (CPU core

→sleep and OSC-Stop →yes) as well as in

the POWER-DOWN (CPU core

→sleep and OSC-Stop →no). All other clock sources

supply no clock signal in SLEEP if NSTOP = 0. The 4-bit counter stages of Timer 2 have

an additional clock output (POUT).

Address: ’7’hex - Subaddress: ’A’hex

Bit 3Bit 2Bit 1Bit 0

WDC

WDL

WDR

WDT1

WDT0

Reset value: 1111b

WDL

WatchDog Lock mode

WDL = 1, the watchdog can be enabled and disabled by using the WDR-bit

WDL = 0, the watchdog is enabled and locked. In this mode the WDR-bit has no

effect. After the WDL-bit is cleared, the watchdog is active until a system

reset or power-on reset occurs.

WDR

WatchDog Run and stop mode

WDR = 1, the watchdog is stopped/disabled

WDR = 0, the watchdog is active/enabled

WDT1

WatchDog Time 1

WDT0

WatchDog Time 0

Table 14. Watchdog Time Control Bits

WDT1

WDT0

Divider

Delay Time to Reset with

in = 1/32 kHz

Delay Time to Reset with

in = 1/(2/1 MHz)

512

15.625 ms

0.256 ms/0.512 ms

2048

62.5 ms

1.024 ms/2.048 ms

16384

0.5 s

8.2 ms/16.4 ms

131072

4 s

65.5 ms/131 ms

ATAR080 Datasheet(PDF) 30 Page - ATMEL Corporation

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