PCA9506DGG datasheet(15/30 Pages) PHILIPS

15 / 30 page

9397 750 14939

Product data sheet

Rev. 01 — 14 February 2006

15 of 30

Philips Semiconductors

PCA9506

40-bit I2C-bus I/O port with RESET, OE, and INT

8.3 Acknowledge

The number of data bytes transferred between the START and the STOP conditions from

transmitter to receiver is not limited. Each byte of eight bits is followed by one

acknowledge bit. The acknowledge bit is a HIGH level put on the bus by the transmitter,

whereas the master generates an extra acknowledge related clock pulse.

A slave receiver which is addressed must generate an acknowledge after the reception of

each byte. Also a master must generate an acknowledge after the reception of each byte

that has been clocked out of the slave transmitter. The device that acknowledges has to

pull down the SDA line during the acknowledge clock pulse, so that the SDA line is stable

LOW during the HIGH period of the acknowledge related clock pulse; set-up and hold

times must be taken into account.

A master receiver must signal an end of data to the transmitter by not generating an

acknowledge on the last byte that has been clocked out of the slave. In this event, the

transmitter must leave the data line HIGH to enable the master to generate a STOP

condition.

8.4 Bus transactions

Data is transmitted to the PCA9506 registers using Write Byte transfers (see Figure 11,

Figure 12, and Figure 13). Data is read from the PCA9506 registers using Read and

Receive Byte transfers (see Figure 14).

Fig 9.

System conﬁguration

002aaa966

MASTER

TRANSMITTER/

RECEIVER

SLAVE

RECEIVER

SLAVE

TRANSMITTER/

RECEIVER

MASTER

TRANSMITTER

MASTER

TRANSMITTER/

RECEIVER

SDA

SCL

I2C-BUS

MULTIPLEXER

SLAVE

Fig 10. Acknowledgement on the I2C-bus

002aaa987

START

condition

clock pulse for

acknowledgement

not acknowledge

acknowledge

data output

by transmitter

data output

by receiver

SCL from master

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