9397 750 14939

© Koninklijke Philips Electronics N.V. 2006. All rights reserved.

Product data sheet

Rev. 01 — 14 February 2006

21 of 30

Philips Semiconductors

PCA9506

12. Dynamic characteristics

[1]

Minimum SCL clock frequency is limited by the bus time-out feature, which resets the serial bus interface if either SDA or SCL is held

LOW for a minimum of 25 ms. Disable bus time-out feature for DC operation.

[2]

[3]

[4]

bridge the undefined region SCL’s falling edge.

Table 11:

Dynamic characteristics

Symbol

Parameter

Conditions

Standard mode

Unit

Min

Max

Min

Max

SCL clock frequency

[1]

0

100

0

400

kHz

bus free time between a STOP and

START condition

4.7

-

1.3

-

µs

hold time (repeated) START

condition

4.0

-

0.6

-

µs

set-up time for a repeated START

condition

4.7

-

0.6

-

µs

set-up time for STOP condition

4.0

-

0.6

-

µs

data hold time

0

-

0

-

ns

data valid acknowledge time [2]

0.1

3.45

0.1

0.9

µs

data valid time [3]

0.1

3.45

0.1

0.9

µs

data set-up time

250

-

100

-

ns

LOW period of the SCL clock

4.7

-

1.3

-

µs

HIGH period of the SCL clock

4.0

-

0.6

-

µs

fall time of both SDA and SCL

signals

[4] [5]

-

300

300

ns

rise time of both SDA and SCL

signals

[4] [5]

-

1000

300

ns

pulse width of spikes that must be

suppressed by the input filter

[7]

-

50-50

ns

Port timing

enable time

output

-

80

-

80

ns

disable time

output

-

40

-

40

ns

data output valid time

-

250

-

250

ns

data input setup time

100

-

100

-

ns

data input hold time

0.5

-

0.5

-

µs

Interrupt timing

valid time on pin INT_N

-

4

-

4

µs

reset time on pin INT_N

-

4

-

4

µs

Reset

reset pulse width

4

-

4

-

ns

reset recovery time

0

-

0

-

ns

reset time

100

-

100

-

ns