SP40T datasheet(35/71 Pages) INFINEON

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Data Sheet

Revision1.1

2020-05-14

SP40T

Tire Pressure Monitoring Sensor

Functional Descriptions

In program- and debug-mode where the device is controlled by I2C the firmware I2C handler resets the watchdog.

Since in idle state no application code can be executed, idle state must not take longer than the watchdog time-

out period.

Associated register:

•CFG2 (bit WDRES for resetting watchdog)

5.5.3

Hardware CRC

The SP40T comes with a hardware CRC module. This module calculates a 16 bit CRC value of an arbitrary

sequence of bytes in accordance with the CRC-CCITT (CRC16) standard, i.e. using the polynomial 0x1021. As start

value for CRC calculation 0xFFFF should be used, however the CRC module may be initialized with other start

values as well.

The CRC module is used by the firmware I2C handler which checks the CRC value of incoming I2C commands and

calculates the CRC value for outgoing telegrams.

CRC of a sequence of data bytes

The CRC module can be used in application code as well. For this end the start value 0xFF must be loaded into the

two CRC registers CRC1 and CRC0, respectively. Then the data bytes are written subsequently into the CRC data

The flag CRCVALID is set automatically if the result is zero, i.e. CRC1 and CRC0 are both zero. This flag can be used

for simply checking the CRC of incoming telegrams by initializing CRC1 and CRC0 with 0xFF, then subsequently

writing the data bytes and the two CRC bytes of the telegram to the CRC data register. If there is no bit error in the

telegram the result is zero and CRCVALID is set.

CRC of a serial bit-stream

The CRC hardware can also be used for calculation of the CRC of a serial bit-stream. The bit CRCSD is the input for

the serial bit-stream. The bit CRCSS is the corresponding strobe signal.

As for byte processing the result registers CRC1 and CRC0 must be initialized with 0xFF, respectively. After writing

a bit into CRCSD, bit CRCSS has to be set and reset by software. Then the next bit is written into CRCSD and so on.

If a bit-stream is longer than 8 bit, serial and byte-wise CRC encoding can be mixed. As long as more than 8 bits

are left, data can be written byte-wise into the CRC data register. Finally, the residual bits are processed using

CRCSD and CRCSS.

With hardware CRC associated registers:

• CRCC (bits CRCSD, CRCSS, CRCVALID)

•CRCD

•CRC0

•CRC1

5.5.4

I²C Controller

The SP40T features a slave hardware I2C interface with the fixed device address 0x6C. When the I2C is activated,

pin PP0 is configured as input and serves as clock line (SCL). Pin PP1 is initialized as input, too, and serves as data

line (SDA). Both lines need a pull-up resistor, either an external resistor or by activating the internal pull-up

resistors. The active device transmits data by pulling the data line low.

In program- and debug- mode the I2C interface is managed by a firmware I2C handler. Only certain I2C commands

are available in these modes, no application code can be executed. The internal pull-up resistors are enabled by

the I2C handler.

SP40T Datasheet(PDF) 35 Page - Infineon Technologies AG

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