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PIC16F616-E/ML Datasheet(PDF) 12 Page - Cirrus Logic |
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PIC16F616-E/ML Datasheet(HTML) 12 Page - Cirrus Logic |
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12 / 172 page  PIC16F616/16HV616 DS41288A-page 10 Preliminary © 2006 Microchip Technology Inc. TABLE 2-2: PIC16F616/16HV616 SPECIAL FUNCTION REGISTERS SUMMARY BANK 1 Addr Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Page Bank 1 80h INDF Addressing this location uses contents of FSR to address data memory (not a physical register) xxxx xxxx 17, 104 81h OPTION_REG RAPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 12, 104 82h PCL Program Counter’s (PC) Least Significant Byte 0000 0000 17, 104 83h STATUS IRP(1) RP1(1) RP0 TO PD ZDC C 0001 1xxx 11, 104 84h FSR Indirect Data Memory Address Pointer xxxx xxxx 17, 104 85h TRISA — — TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 --11 1111 25, 104 86h — Unimplemented — — 87h TRISC — — TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 --11 1111 33, 104 88h — Unimplemented — — 89h — Unimplemented — — 8Ah PCLATH — — — Write Buffer for upper 5 bits of Program Counter ---0 0000 17, 104 8Bh INTCON GIE PEIE T0IE INTE RAIE T0IF INTF RAIF 0000 0000 13, 104 8Ch PIE1 — ADIE CCP1IE C2IE C1IE —TMR2IE TMR1IE -000 0-00 14, 104 8Dh — Unimplemented — — 8Eh PCON — — — — — —POR BOR ---- --qq 16, 104 8Fh — Unimplemented — — 90h OSCTUNE — — — TUN4 TUN3 TUN2 TUN1 TUN0 ---0 0000 23, 104 91h ANSEL ANS7 ANS6 ANS5 ANS4 ANS3 ANS2 ANS1 ANS0 1111 1111 26, 104 92h PR2 Timer2 Module Period Register 1111 1111 47, 105 93h — Unimplemented — — 94h — Unimplemented — — 95h WPUA(2) — — WPUA5 WPUA4 — WPUA2 WPUA1 WPUA0 --11 -111 27, 105 96h IOCA — — IOCA5 IOCA4 IOCA3 IOCA2 IOCA1 IOCA0 --00 0000 27, 105 97h — Unimplemented — — 98h — Unimplemented — — 99h SRCON0 SR1 SR0 C1SEN C2REN PULSS PULSR — SRCLKEN 0000 00-0 59, 105 9Ah SRCON1 SRCS1 SRCS2 — — — — — — 00-- ---- 59, 105 9Bh — Unimplemented — — 9Ch — Unimplemented — — 9Dh — Unimplemented — — 9Eh ADRESL Least Significant 2 bits of the left shifted result or 8 bits of the right shifted result xxxx xxxx 72, 105 9Fh ADCON1 — ADCS2 ADCS1 ADCS0 — — — — -000 ---- 71, 105 Legend: – = Unimplemented locations read as ‘0’, u = unchanged, x = unknown, q = value depends on condition, shaded = unimplemented Note 1: IRP and RP1 bits are reserved, always maintain these bits clear. 2: RA3 pull-up is enabled when MCLRE is ‘1’ in the Configuration Word register. |
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