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PIC16F616-E/ML Datasheet(PDF) 37 Page - Cirrus Logic

Part # PIC16F616-E/ML
Description  14-Pin Flash-Based, 8-Bit CMOS Microcontrollers
PDF  172 Pages
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Manufacturer  APEX [Cirrus Logic]
Direct Link  http://www.cirrus.com
Logo APEX - Cirrus Logic

PIC16F616-E/ML Datasheet(HTML) 37 Page - Cirrus Logic

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© 2006 Microchip Technology Inc.
Preliminary
DS41288A-page 35
PIC16F616/16HV616
4.3.5
RC4/C2OUT/P1B
The RC4 is configurable to function as one of the
following:
• a general purpose I/O
• a digital output from Comparator C2
• a digital output from the Enhanced CCP
FIGURE 4-9:
BLOCK DIAGRAM OF RC4
4.3.6
RC5/CCP1/P1A
The RC5 is configurable to function as one of the
following:
• a general purpose I/O
• a digital input/output for the Enhanced CCP
FIGURE 4-10:
BLOCK DIAGRAM OF RC5
PIN
TABLE 4-2:
SUMMARY OF REGISTERS ASSOCIATED WITH PORTC
Note:
Enabling both C2OUT and P1B will cause
a conflict on RC4 and create unpredictable
results. Therefore, if C2OUT is enabled,
the ECCP can not be used in Half-Bridge
or Full-Bridge mode and vice-versa.
I/O Pin
VDD
VSS
D
Q
CK
Q
D
Q
CK
Q
Data Bus
WR
PORTC
WR
TRISC
RD
TRISC
RD
PORTC
0
1
Note
1:
Port/Peripheral Select signals selects between
Port data and peripheral output.
C2OE
CCP1M<3:0>
C2OE
C2OUT
CCP1M<3:0>
CCPOUT/P1B
I/O Pin
VDD
VSS
D
Q
CK
Q
D
Q
CK
Q
Data bus
WR
PORTC
WR
TRISC
RD
TRISC
To Enhanced CCP
RD
PORTC
0
1
CCP1OUT/
CCP1OUT
Enable
P1A
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on:
POR, BOR
Value on
all other
Resets
ANSEL
ANS7
ANS6
ANS5
ANS4
ANS3
ANS2
ANS1
ANS0
1111 1111
1111 1111
CCP1CON
P1M1
P1M0
DCB1
DCB0
CCP1M3
CCP1M2
CCP1M1
CCP1M0
0000 0000
0000 0000
CM1CON0
C1ON
C1OUT
C1OE
C1POL
—
C1R
C1CH1
C1CH0
0000 -000
0000 -000
CM2CON0
C2ON
C2OUT
C2OE
C2POL
—
C2R
C2CH1
C2CH0
0000 -000
0000 -000
PORTC
—
—
RC5
RC4
RC3
RC2
RC1
RC0
--xx 00xx
--uu 00uu
TRISC
—
—
TRISC5
TRISC4
TRISC3
TRISC2
TRISC1
TRISC0
--11 1111
--11 1111
Legend:
x
= unknown, u = unchanged, – = unimplemented locations read as ‘0’. Shaded cells are not used by PORTC.



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