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PIC16F616-E/ML Datasheet(PDF) 33 Page - Cirrus Logic |
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PIC16F616-E/ML Datasheet(HTML) 33 Page - Cirrus Logic |
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33 / 172 page ![]() © 2006 Microchip Technology Inc. Preliminary DS41288A-page 31 PIC16F616/16HV616 4.2.4.6 RA5/T1CKI/OSC1/CLKIN Figure 4-6 shows the diagram for this pin. The RA5 pin is configurable to function as one of the following: • a general purpose I/O • a Timer1 clock input • a crystal/resonator connection • a clock input FIGURE 4-6: BLOCK DIAGRAM OF RA5 VDD VSS D Q CK Q D Q CK Q D Q CK Q D Q CK Q VDD D EN Q D EN Q Weak Data Bus WR WPUA RD WPUA RD PORTA WR PORTA WR TRISA RD TRISA WR IOCA RD IOCA To Timer1 INTOSC Mode RD PORTA INTOSC Mode RAPU OSC2 Note 1: Timer1 LP Oscillator enabled. TMR1LPEN(1) Interrupt-on- Change Oscillator Circuit Q3 I/O Pin |
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