OV8610/OV8110
SINGLE IC CMOS VGA DIGITAL CAMERAS
OmniVision Technologies, Inc. 930 Thompson Place Sunnyvale, CA 94085 U.S.A.
Tel: (408) 733-3030 Fax: (408) 733-3061
e-mail: info@ovt.com
Website: http://www.ovt.com
Version 1.3, August 27, 2001
Page 19
Sub-
address
(hex)
Register
Default
(hex)
Read/
Write
Descriptions
15
COMD
01
RW
Common Control D
COMD[7] – ADC clock 50% duty cycle selection. “1” – 50% duty cycle, “0” –
non 50%.
COMD[6] – PCLK polarity selection. “0” - OV8610/OV8110 output data at PCLK
falling edge and data bus will be stable at PCLK rising edge; “1” - rising edge
output data and stable at PCLK falling edge.
COMD[5] – Digital 2x PLL disable. “1” – disable. “0” – enable.
COMD[4] – Array vertical 2
nd stage skip mode enable. Frame rate will double
and only effective at progressive scan and 1
st stage sub-sampling disable.
COMD[3] – AGCEN pin option. “1” – AGCEN as data output enable/disable pin
control, “0” – normal AGCEN pin.
COMD[2] – Reserved
COMD[1] – Enable NTSC timing. Only part of full resolution output.
COMD[0] – U V digital output sequence exchange control. 1 - UV UV ··· for 16-
bit, U Y V Y ··· for 8-bit; 0 - V U V U ··· for 16-bit and V Y U Y ··· for 8-bit.
Note: COMD[0] is not programmable on the OV8110 image sensor.
16
FSD
03
RW
Field slot division
FSD[7:2] – Field interval selection. It has functional in EVEN and ODD mode
defined by FSD[1:0]. It is disabled in OFF and FRAME mode. The purpose of
FSD[7:2] is to divide the video signal into programmed number of time slots,
and allows HREF to be active only one field in every FSD[7:2] fields. It does
not affect the video data or pixel rate. FSD[7:2]=1 outputs one field every
field. FSD[7:2]=2 outputs one field every two fields. All other fields output
black reference.
FSD[1:0] – field mode selection. Each frame consists of two fields: Odd and
Even, FSD[1:0] define the assertion of HREF in relation to the two fields.
“00” – OFF mode; HREF is not asserted in both fields, one exception is the
single frame transfer operation (see the description for the register 13)
“01” – Interlace mode: ODD mode; HREF is asserted in odd field only.
Progressive mode: HREF is asserted in frame according FD[7:2]
“10” – Interlace mode: EVEN mode; HREF is asserted in even field only.
Progressive mode: HREF is asserted in frame according FD[7:2].
“11” – FRAME mode; HREF is asserted in both odd field and even field.
FSD[7:2] disabled.
17
HREFST
38
RW
Horizontal HREF start
HS[7:0] – selects the starting point of HREF window, each LSB represents four
pixels for SVGA resolution mode, two pixels for QVGA resolution mode, one
pixel for QCIF mode. This value is set based on an internal column counter.
The default value corresponds to 800 horizontal windows. Maximum window
size is 824. HS[7:0] should be less than HE[7:0].
18
HREFEND
EA
RW
Horizontal HREF end
HE[7:0] – selects the ending point of HREF window, each LSB represents four
pixels for full resolution and two pixels for QSVGA resolution, one pixel for
QCIF mode. This value is set based on an internal column counter, the
default value corresponds to the last available pixel. HE[7:0] should be larger
than HS[7:0]. See window description below.
19
VSTRT
03
RW
Vertical line start
VS[7:0] – selects the starting row of vertical window, in full resolution mode,
each LSB represents 2 scan line in one field for Interlaced Scan Mode, 4
scan line in one frame for Progressive Scan Mode. In QSVGA mode, each
LSB represents 1 scan line in one field for Interlaced Mode, 2 scan line in one
frame for Progressive Scan Mode. See window description below. Min. is
[02], max. is [98] and should less than VE[7:0].
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