Advanced Information
Preliminary
OV8610/OV8110
OV8610 SINGLE-CHIP CMOS VGA COLOR DIGITAL CAMERA
OV8110 SINGLE-CHIP CMOS VGA B&W DIGITAL CAMERA
OmniVision Technologies, Inc. 930 Thompson Place Sunnyvale, CA 94085 U.S.A.
Tel: (408) 733-3030 Fax: (408) 733-3061
e-mail: info@ovt.com
Website: http://www.ovt.com
Version 1.3, August 27, 2001
Page 2
Pin Description
Table 1. Pin Description
Pin No.
Name
Pin Type
Function/Description
01
SVDD
VIN
Array power (+3.3VDC). Bypass to ground with a 0.1
µF capacitor.
02
RESET
Function
(Default=0)
Chip reset, active high. Resets all control registers to factory defaults.
03
AGCEN
Function
(Default=0)
Automatic Gain Control (AGC) selection
“0” – Disable AGC
“1” – Enable AGC
Note: This function is disabled when OV8610/OV8110 sensor is configured in
SCCB low mode. In SCCB low mode this pin is an SCCB chip select function.
04
FREX
Function
(Default=0)
Frame exposure control
“0” – Disables frame exposure control
“1” – Enables frame exposure control
05
VREQ
VREF (1.5V)
Array reference. Connect to ground with a 0.1
µF (min.) capacitor.
06
ASUB
VIN
Analog substrate voltage
07
AGND
VIN
Analog ground
08
AVDD
VIN
Analog power supply (+3.3VDC). Bypass to ground with a 0.1
µF capacitor.
09
PWDN
Function
(Default=0)
Power-down mode selection.
“0” – Operating mode
“1” – Power-down mode
10
HVDD
VREF (5.0V)
Charge pump out voltage. Doubler must be enabled.
11
VCCHG
VREF (2.7V)
Internal voltage reference. Bypass to ground with a 0.1
µF capacitor.
12
SCCBB
Function
(Default=0)
SCCB enable selection.
“0” – Selects internal register setting control and enables SCCB interface
“1” – Enables I/O input pin power on latch setting control
13
VTO
O
B&W CCIR analog composite signal output—for test purposes only
14
ADVDD
VIN
Analog power supply (+3.3VDC). Bypass to ground with a 0.1
µF capacitor.
15
ADGND
VIN
Analog signal ground
16
VSYNC/CSYS
O
Vertical sync output. At power-up, read as CSYS.
17
FODD/SRAM
O
Field ID FODD output. At power-up, read as SRAM.
18
HREF/VSFRAM
O
HREF output. At power-up, read as VSFRAM
19
*UV7/B8
O
Bit 7 of U video component output. At power-up, sampled as B8.
20
*UV6/TVEN
O
Bit 6 of U video component output. At power-up, sampled as TVEN.
21
*UV5/MIR
O
Bit 5 of U video component output. At power-up, sampled as MIR.
22
*UV4/SLAEN
O
Bit 4 of U video component output. At power-up, sampled as SLAEN.
23
*UV3/ECLK0
O
Bit 3 of U video component output. At power-up, samples as ECLKO.
24
*UV2/QSVGA
O
Bit 2 of U video component output. At power-up, sampled as QSVGA.
25
*UV1/CC656
O
Bit 1 of U video component output. At power-up, sampled as CC656.
26
*UV0/GAMMA
O
Bit 0 of U video component output. At power-up, sampled as GAMMA.
27
XCLK1
I
Crystal clock input
28
XCLK2
O
Crystal clock output
29
DVDD
VIN
Digital power supply (+3.3VDC). Bypass to ground with a 0.1
µF capacitor.
30
DGND
VIN
Digital ground
31
DOGND
VIN
Digital interface output buffer ground
32
DOVDD
VIN
Digital output buffer supply (+3.3VDC ). Bypass to ground with a 0.1
µF capacitor.
33
PCLK/PWDB
O
PCLK output. At power-up sampled as charge pump enable.
34
Y7
O
Bit 7 of Y video component output
35
Y6
O
Bit 6 of Y video component output
36
Y5/SHARP
O
Bit 5 of Y video component output. At power-up, sampled as SHARP.
37
Y4
O
Bit 4 of Y video component output
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