TPS38 datasheet(5/53 Pages) TI

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Table 6-1. Pin Functions

NAME

WSON

(DSK)

SOT23

(DYY)

I/O

DESCRIPTION

NUM.

VDD

Input Supply Voltage: Bypass with a 0.1 µF capacitor to GND.

SENSE1

This pin is connected to the voltage that will be monitored for fixed variants or to a resistor divider

for the adjustable variant. Depending on the SENSE1 sensing configuration, when the voltage on

SENSE1 pin detects an undervoltage (UV) or an overvoltage (OV) fault, RESET1/RESET1 asserts

after the sense time delay, set by CTS1. When the voltage on the SENSE1 pin transitions back to

an unfaulty UV or OV state, RESET1/RESET1 deasserts after the reset time delay, set by CTR1. For

noisy applications, placing a 10 nF to 100 nF ceramic capacitor close to this pin may be needed for

optimum performance.

SENSE2

This pin is connected to the voltage that will be monitored for fixed variants or to a resistor divider

for the adjustable variant. Depending on the SENSE2 sensing configuration, when the voltage on

SENSE2 pin detects an undervoltage (UV) or an overvoltage (OV) fault, RESET2/RESET2 asserts

after the sense time delay, set by CTS2. When the voltage on the SENSE2 pin transitions back to

an unfaulty UV or OV state, RESET2/RESET2 deasserts after the reset time delay, set by CTR2. For

noisy applications, placing a 10 nF to 100 nF ceramic capacitor close to this pin may be needed for

optimum performance.

RESET1/

RESET1

Output Reset Signal For Channel 1: See Section 5 for output topology options. RESET1/RESET1

asserts when SENSE1 detects an undervoltage or overvoltage fault condition. RESET1/RESET1

remains asserted for the reset time delay period after SENSE1 transitions out of an UV or OV fault

condition. For active low open-drain reset output, an external pullup resistor is required. Do not place

external pullup resistors on push-pull outputs.

Reset output signal for: SENSE1

Sensing Topology: Undervoltage (UV) or Overvoltage (OV)

Output topology: Open Drain or Push Pull, Active Low or Active High

RESET2/

RESET2

Output Reset Signal For Channel 2: See Section 5 for output topology options. RESET2/RESET2

asserts when SENSE2 detects an undervoltage or overvoltage fault condition. RESET2/RESET2

remains asserted for the reset time delay period after SENSE2 transitions out of an UV or OV fault

condition. For active low open-drain reset output, an external pullup resistor is required.

Reset output signal for: SENSE2

Sensing Topology: Undervoltage (UV) or Overvoltage (OV)

Output topology: Open Drain, Active Low or Active High

CTR1/ MR

Channel 1 RESET Time Delay: User-programmable reset time delay for RESET1/RESET1. Connect

an external capacitor for adjustable time delay or leave the pin floating for the shortest delay.

Manual Reset: If this pin is driven low, the RESET1/RESET1 output will reset and become asserted.

The pin can be left floating or be connected to a capacitor. This pin should not be driven high.

CTR2/ MR

Channel 2 RESET Time Delay: User-programmable reset time delay for RESET2/RESET2. Connect

an external capacitor for adjustable time delay or leave the pin floating for the shortest delay.

Manual Reset: If this pin is driven low, the RESET2/RESET2 output will reset and become asserted.

The pin can be left floating or be connected to a capacitor. This pin should not be driven high.

GND

8, 13

Ground. All GND pins must be electrically connected to the board ground.

PAD

2, 5, 14

The PAD for the DSK package is not internally connected, the PAD can be connected to GND or be

left floating. For the DYY package, NC stands for “No Connect”. The pins are to be left floating.

CTS1

Channel 1 SENSE Time Delay: Capacitor programmable sense delay: CTS1 pin offers a user-

adjustable sense delay time when asserting a reset condition. Connecting this pin to a ground-

referenced capacitor sets the RESET1/RESET1 delay time to assert.

CTS2

Channel 2 SENSE Time Delay: Capacitor programmable sense delay: CTS2 pin offers a user-

adjustable sense delay time when asserting a reset condition. Connecting this pin to a ground-

referenced capacitor sets the RESET2/RESET2 delay time to assert.

www.ti.com

TPS38-Q1

SNVSBI8C – AUGUST 2020 – REVISED DECEMBER 2021

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