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8.3.3 Output Logic Configurations

TPS38-Q1 has two channels with separate sense pins and reset pins that can be configured independently of

each other. Channel 1 is available as Open-Drain and Push-Pull while channel 2 is only available as Open-Drain

topology.

The available output logic configuration combinations are shown in Table Table 8-2.

Table 8-2. TPS38-Q1 Output Logic

DESCRIPTION

NOMENCLATURE

VALUE

GPN

TPS38-Q1 (+ topology)

CHANNEL 1

CHANNEL 2

Topology (OV and UV only)

both channels are either OV or

•

UV = Undervoltage

•

OV = Overvoltage

•

PP = Push-Pull

•

OD = Open-Drain

•

L = Active low

•

H = Active high

TPS38A-Q1

UV OD L

TPS38B-Q1

UV PP L

UV OD L

TPS38D-Q1

UV PP L

UV OD H

TPS38E-Q1

UV PP H

UV OD H

TPS38F-Q1

UV PP H

UV OD L

TPS38G-Q1

UV OD H

TPS38H-Q1

UV OD H

UV OD L

TPS38J-Q1

OV OD L

TPS38K-Q1

OV OD H

TPS38L-Q1

OV OD H

OV OD L

TPS38M-Q1

OV PP L

OV OD L

TPS38N-Q1

OV PP L

OV OD H

TPS38O-Q1

OV PP H

OV OD H

TPS38P-Q1

OV PP H

OV OD L

8.3.3.1 Open-Drain

Open-drain output requires an external pull-up resistor to hold the voltage high to the required voltage logic.

Connect the pull-up resistor to the proper voltage rail to enable the output to be connected to other devices at

the correct interface voltage levels.

To select the right pull-up resistor consider system VOH and the (Ilkg) current provided in the electrical

characteristics, high resistors values will have a higher voltage drop affecting the output voltage high. The

open-drain output can be connected as a wired-AND logic with other open-drain signals such as another

TPS38-Q1 open-drain output pin.

8.3.3.2 Push-Pull

Push-Pull output does not require an external resistor since is the output is internally pulled-up to VDD during

VOH condition and output will be connected to GND during VOH condition.

8.3.3.3 Active-High (RESET)

RESET (active-high), denoted with no bar above the pin label. RESET remains low (VOL, deasserted) as long as

sense voltage is in normal operation within the threshold boundaries and VDD voltage is above UVLO. To assert

a reset sense pins needs to meet the condition below:

• For undervoltage variant the SENSE voltage need to cross the lower boundary (VITN).

• For overvoltage variant the SENSE voltage needs to cross the upper boundary (VITP).

TPS38-Q1

SNVSBI8C – AUGUST 2020 – REVISED DECEMBER 2021

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