over multiple frequency bins. This feature greatly improves the emissions performance of the entire power

supply block and hence relieves the system designer from one major concern in isolated power supply design.

8.3.5 Slew Rate Control

the strength of the driver of PowerFETs turning on. As shown in Figure 8-7 below, the slew rate of the switching

edges is controllable with the resistor. Rolling off harmonics through slew rate control can eliminate the need for

shielding and common mode chokes in many applications.

When the feature slows down the charging and discharging of the gate capacitance, the extended transition

times of the FETs increases the transition losses during each switching cycle. This increases power dissipation,

which decreases efficiency and exacerbates thermal concerns. This will limit how much the slew rate can be

reduced. Another cost is the peak current of each cyle will be increased. It is because the slow edges reduce the

load on each cycle.

SR2

SR1

Figure 8-7. Slew Rate Control Scheme

and the slew rate for 12 V and 24 V cases are listed in Table 8-2 below. As the slew rate is independent of

the switching frequency, care must be taken that at high frequencies, the slew rate should be fast enough to

maximize the output power delivery to the load. If the SR pin is left floating, the slew rate will be set to the default

value. An SR pin short to GND is read as a fault condition, and the device will stop switching.

Table 8-2. Slew Rate Control Look-up Table

VCC (V)

Typical SLEW RATE (V/μs)

5

4.8

337

5

Floating (Default)

263

5

15

224

5

21

198

12

4.8

424

12

Floating (Default)

298

12

15

237

12

21

199

24

4.8

583

SN6507

SLLSFM0A – MARCH 2022 – REVISED JUNE 2022

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