LT3755 datasheet(20/30 Pages) AD

20 / 30 page

LT8355-1

Rev. 0

For more information www.analog.com

APPLICATIONS INFORMATION

NMOS switch and Schottky rectifier. The gate-source volt-

age rating should be higher than 12V. The drain current

rating should be sufficient to conduct the full programmed

LED current with some margin. Ensure that the PWMTG

drive voltage of 8.5V will fully enhance the PMOS device.

Be careful when selecting a PMOS to consider the effect

that higher current ratings have on gate charge (Qg). A

very high Qg PMOS will slow turn-on and turn-off times

and can lead to offsets for very brief on-time PWM dim-

ming (shorter than 500ns). A clamping diode might be

necessary near PMOS’s drain to prevent the drain ringing

well below ground when being shorted to ground through

a long cable.

Power NMOS Selection

Choose an external NMOS switch with breakdown volt-

age higher than the programmed output voltage by at

least 20%. Select the forward current rating based on

the load requirements and maximum current through the

switch. Be sure to set the programmable switch current

limit lower than the maximum rated forward current of

the switch. Like the power PMOS, the gate charge of the

external NMOS can impact performance. Very low Qg

MOSFETs (<1nC) can turn on quickly, potentially nega-

tively impacting EMI performance. Conversely, very high

Qg MOSFETs (>100nC) can draw excessive current from

the part’s internal LDO regulator at higher switching

frequencies.

Sense Resistors Selection

Select the LED and switch current sense resistors for

power dissipation limits and PCB footprint convenience.

The control loop will limit the steady state voltage dropped

across the LED current sense resistor to 250mV (typical)

and the switch current sense resistor to 100mV (typical).

Large footprint resistors such as 2010 may be needed

for high power applications. Be sure to Kelvin all sense

resistors connections to the LT8355-1.

LED Fault Events

LT8355-1 provides a variety of fault detection to mitigate

damage to external components. While LT8355-1 has

many self-protection features, three LED types of faults

(LED Short, Overvoltage and LED Overcurrent) will cause

the part to immediately stop switching and, if an exter-

nal PMOS is used according to instructions in the PWM

Dimming section, disconnect the load from the output

capacitor.

The LED overcurrent fault detection uses the LED current

sense resistor RILED. If the voltage drop across the sense

resistor is greater than 670mV (typical), an internal fault

signal gets asserted. The LED Short fault senses load

voltage. This can allow the detection of limited failures,

such as one or two of the LEDs in a string becoming

shorted. LT8355-1 senses the voltage at the FB pin and

detects a LED Short fault if that voltage falls below 300mV

(typical, excluding during start-up). It is important to note

that the FB resistor divider must be in place to use the

LED Short fault detection. For configurations where the

VISP-ISN is set lower than 75mV (typ), the FB LED Short

can latch LT8355-1 in a permanent start-up cycle fail-

ing to reach steady-state. To defeat this behavior at start

up several options exists: the VISP-ISN setting must be

temporarily higher until start up finishes, using a higher

VISP-ISN and lower PWM pin voltage setting to achieve

same light intensity, or defeat LED short by forcing FB

pin to be at least 400mV for all input voltage conditions.

After a successful start up, LT8355-1 can regulate VISP-ISN

to any setting provided that FB pin voltage stays above

LED Short threshold. The Overvoltage fault occurs when

the voltage at the FB pin exceeds 1.26V (typical). The FB

resistor divider must be in place to take advantage of

the over voltage fault protection. LT8355-1 clears faults

and resumes switching depending on the type of fault.

Switching resumes as soon as an overvoltage fault has

cleared.

Recovery from Short LED and LED Overcurrent faults will

enter soft-start as if it had just been turned on via the EN/

UVLO pin. Upon successful completion of the soft-start

process with no faults, the internal fault clears and normal

operation resumes. The PWM dimming logic falling edge

is ignored for both internal and external PWM until soft-

start is complete or the control loop approaches steady

state. Table 4 summarizes operating conditions that can

trigger a fault, and/or turn off switching at the PWMTG1,2

and GATE1,2 pins.

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