F2934 Datasheet

X0010823

Rev.1.1

Apr 28, 2021

Page 4

1.

Pin Information

1.1

Pin Assignments

VCTL

1

4

3

2

RFC

GND

GND

GND

E.P.

12

9

10

11

RF1

GND

RF2

50

Ω

50

Ω

1.2

Pin Descriptions

Table 1. Pin Descriptions

Pin Number

Pin Name

Description

1

VCTL

Controls the selected path when EN is low. It is disabled when EN is logic high (see

Table 2).

2, 4, 6, 7, 8, 10,

11, 13, 14, 15

GND

Ground. Also, internally connected to the ground paddle. Ground this pin as close to the

device as possible.

3

RFC

RF Common Port. Matched to 50Ω when one of the two RF ports is selected. If this pin

is not 0V DC then an external coupling capacitor must be used.

5

EN

EN as a logic low allows VCTL to control the selected switch path. With EN set to logic

high puts the part in all paths off state and disables the control of VCTL (Table 2).

9

RF1

RF1 Port. Matched to 50Ω. If this pin is not 0V DC, then an external coupling capacitor

must be used.

12

RF2

RF2 Port. Matched to 50Ω. If this pin is not 0V DC, then an external coupling capacitor

must be used.

16

VDD

Power Supply. Bypass to GND with capacitors shown in the Typical Application Circuit

as close as possible to pin.

EP

Exposed Pad. Internally connected to GND. Solder this exposed pad to a PCB pad that

uses multiple ground vias to provide heat transfer out of the device and into the PCB

ground planes. These multiple ground vias are also required to achieve the specified

RF performance.