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ESD752 Datasheet(PDF) 5 Page - Texas Instruments |
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ESD752 Datasheet(HTML) 5 Page - Texas Instruments |
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5 / 25 page ![]() 6.6 Electrical Characteristics over TA = 25°C (unless otherwise noted)(1) PARAMETER TEST CONDITIONS DEVICE MIN TYP MAX UNIT VRWM Reverse stand-off voltage ESD752 –24 24 V VBRF Forward breakdown voltage(2) IIO = 10 mA, IO to GND ESD752 25.5 35.5 V VBRR Reverse breakdown voltage(2) IIO = –10 mA, IO to GND ESD752 –35.5 –25.5 V VCLAMP Clamping voltage(4) IPP = 5.7 A, tp = 8/20 µs, IO to GND ESD752 37 V Clamping voltage(5) IPP = 16 A, TLP, IO to GND or GND to IO 35 VHold Holding voltage after snapback(3) TLP ESD752 30 V ILEAK Leakage current VIO = ±24 V, IO to GND ESD752 -50 5 50 nA RDYN Dynamic resistance(5) IO to GND ESD752 0.35 Ω GND to IO 0.35 CL Line capacitance(6) VIO = 0 V, f = 1 MHz, Vpp = 30 mV ESD752 3 5 pF (1) Measurements made on both IO channels. (2) VBRF and VBRR are defined as the voltage when ± 10 mA is applied in the positive or negative direction respectively, before the device latches into the snapback state. (3) VHOLD is defined as the lowest voltage on the TLP plot once the trigger threshold is reached and the device snapbacks and begins clamping the voltage. (4) Device stressed with 8/20 μs exponential decay waveform according to IEC 61000-4-5. (5) Non-repetitive current pulse, Transmission Line Pulse (TLP); square pulse; ANSI / ESD STM5.5.1-2008. (6) Measured from IO to GND on both channels. www.ti.com ESD752 SLVSGX0A – MAY 2022 – REVISED AUGUST 2022 Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 5 Product Folder Links: ESD752 |
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