8.2.3 Detailed Design Procedure

that can occur when one of the USB-PD slower speed lines (CC1, CC2, SBU1, SBU2, D+, and D-) is shorted

to VBUS. The bidirectional characteristic ensures both positive and negative polarity are protected. The low 1.7

pF capacitance of the ESD7x2 device ensures data rates up to 480 Mbps, which allows the designer to meet

making it suitable for protecting the VBUS power rail.

8.2.4 Application Curves

Time(ns)

-100

0

100

200

300

400

500

600

700

-25

0

25

50

75

100

125

150

Vclamp_ESD at 30ns = 28V

Figure 8-2. +8-kV Clamped IEC Waveform

Time(ns)

-100

0

100

200

300

400

500

600

700

-175

-150

-125

-100

-75

-50

-25

0

25

Vclamp_ESD at 30ns = -32.9V

Figure 8-3. −8-kV Clamped IEC Waveform

Time ( s)

-5

0

5

10

15

20

25

30

35

40

0

0

0.5

5

1

10

1.5

15

2

20

2.5

25

3

30

3.5

35

4

40

4.5

45

5

50

5.5

55

6

60

Current

Voltage

Figure 8-4. 8/20 µs Surge Response at 5.7 A

9 Power Supply Recommendations

These are passive TVS diode-based ESD protection devices; therefore, there is no requirement to power it.

Ensure that the maximum voltage specifications for each pin are not violated.

10 Layout

10.1 Layout Guidelines

• The optimum placement is as close to the connector as possible.

– EMI during an ESD event can couple from the trace being struck to other nearby unprotected traces,

resulting in early system failures.

– The PCB designer must minimize the possibility of EMI coupling by keeping any unprotected traces away

from the protected traces which are between the TVS and the connector.

• Route the protected traces as straight as possible.

• Eliminate any sharp corners on the protected traces between the TVS and the connector by using rounded

corners with the largest radii possible.

– Electric fields tend to build up on corners, increasing EMI coupling.

• If pin 3 is connected to ground, use a thick and short trace for this return path.

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ESD752

SLVSGX0A – MAY 2022 – REVISED AUGUST 2022

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