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ESD752 Datasheet(PDF) 6 Page - Texas Instruments |
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ESD752 Datasheet(HTML) 6 Page - Texas Instruments |
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6 / 25 page ![]() 6.7 Typical Characteristics Vclamp (V) 5 10 15 20 25 30 35 40 0 2 4 6 8 10 12 14 16 18 20 22 24 26 28 tp = 100 ns, Transmission Line Pulse (TLP) Figure 6-1. Positive TLP Curve Vclamp (V) 5 10 15 20 25 30 35 40 0 2 4 6 8 10 12 14 16 18 20 22 24 26 28 tp = 100 ns, Transmission Line Pulse (TLP) Figure 6-2. Negative TLP Curve Time(ns) -100 0 100 200 300 400 500 600 700 -25 0 25 50 75 100 125 150 Vclamp_ESD at 30ns = 28V Figure 6-3. +8-kV Clamped IEC Waveform Time(ns) -100 0 100 200 300 400 500 600 700 -175 -150 -125 -100 -75 -50 -25 0 25 Vclamp_ESD at 30ns = -32.9V Figure 6-4. −8-kV Clamped IEC Waveform VR (V) 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 3 3.1 3.2 Frequency = 1MHz, Vpp = 30 mV Figure 6-5. Capacitance vs. Bias Voltage VR (V) -25 -20 -15 -10 -5 0 5 10 15 20 25 -10 -8 -6 -4 -2 0 2 4 6 8 10 TA = 150 C ILEAK is less than 1 nA at -55 C and 25 C. Figure 6-6. Leakage Current vs. Bias Voltage Across Temperature ESD752 SLVSGX0A – MAY 2022 – REVISED AUGUST 2022 www.ti.com 6 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: ESD752 |
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