ESD752 datasheet(9/25 Pages) TI

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7.3.4 Dynamic Resistance

The IO pins feature an ESD clamp that has a low RDYN of 0.35 Ω for the ESD752 device, and 0.57 Ω for the

ESD7x2 device, which prevents system damage during ESD events.

7.3.5 DC Breakdown Voltage

The DC breakdown voltage between the IO pins is a minimum of ± 25.5 V. This ensures that sensitive equipment

is protected from surges above the reverse standoff voltage of ± 24 V.

7.3.6 Ultra Low Leakage Current

The IO pins feature an ultra-low leakage current of 50 nA (maximum) with a bias of ± 24 V.

7.3.7 Clamping Voltage

The IO pins feature an ESD clamp that is capable of clamping the voltage to 37 V (IPP = 5.7 A for 8/20 μs surge

waveform), 35 V (IPP = 16 A for TLP), 36 V (IPP = 1.5 A for 8/20 μs surge waveform), and 38 V (IPP = 16 A for

TLP) for the ESD752 and ESD7x2, respectively.

7.3.8 Industry Standard Leaded Packages

These devices feature industry standard SOT-23 (DBZ) and SC-70 (DCK) leaded packages for automatic optical

inspection (AOI).

7.4 Device Functional Modes

The ESD752 and ESD7x2 are dual channel passive clamp devices that have low leakage during normal

operation when the voltage between IO and GND is below VRWM, and activate when the voltage between IO and

GND goes above VBR. During IEC 61000-4-2 ESD events, transient voltages as high as ±30 kV can be clamped

on either channel. When the voltages on the protected lines fall below the VHOLD, the device reverts back to the

low leakage passive state.

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ESD752

SLVSGX0A – MAY 2022 – REVISED AUGUST 2022

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ESD752 Datasheet(PDF) 9 Page - Texas Instruments