USS820FD datasheet(11/56 Pages) AGERE

11 / 56 page

Agere Systems Inc.

Data Sheet, Rev. 1

August 2004

USB Device Controller

USS-820FD

The USS-820FD is controlled through an asynchronous, read/write register interface. Registers are addressed via

the A[4:0] pins, and control is provided through the RDN, WRN, and IOCSN pins. Reserved bits of registers must

always be written with 0. Writing 1 to these bits may produce undefined results. These bits return undefined values

when read.

A register read is accomplished by placing the register address on the A bus and asserting the IOCSN and RDN

pins. After read data valid (tRDDV), the register data will appear on the D bus. A register write is accomplished by

placing the register address on the A bus and the data to be written on the D bus, and asserting the IOCSN and

WRN pins.

Tables 7 and 8 show alphabetical and numerical listings of all the available special function registers (SFR) for the

USS-820FD. For reference purposes, an alphabetized list of SFR bit names is included in Appendix A. Tables 12—

39 provide details for each of the registers. Some of these registers are replicated for each endpoint. The individ-

ual, endpoint-specific register is selected by the EPINDEX register.

Table 7. Special Function Registers (By Name)

Description

Address

Table

Page

DSAV

Data Set Available

1DH

DSAV1

Data Set Available 1

1EH

EPCON*

* Contains shared bits. See Special Firmware Action for Shared Register Bits section.

† Indexed by EPINDEX.

Endpoint Control Register

0BH†

EPINDEX

Endpoint Index Register

0AH

FADDR

Function Address Register

10H

LOCK

Suspend Power-Off Locking Register

19H

MCSR

Miscellaneous Control/Status Register

1CH

PEND

Pend Hardware Status Update Register

1AH

REV

Hardware Revision Register

18H

RXCNTH

Receive FIFO Byte-Count High Register

07H†

RXCNTL

Receive FIFO Byte-Count Low Register

06H†

RXCON

Receive FIFO Control Register

08H†

RXDAT

Receive FIFO Data Register

05H†

RXFLG

Receive FIFO Flag Register

09H†

RXSTAT*

Endpoint Receive Status Register

0DH†

SBI*

Serial Bus Interrupt Register

14H

SBI1*

Serial Bus Interrupt Register 1

15H

SBIE

Serial Bus Interrupt Enable Register

16H

SBIE1

Serial Bus Interrupt Enable Register 1

17H

SCR

System Control Register

11H

SCRATCH

Scratch Firmware Information Register

1BH

SOFH*

Start of Frame High Register

0FH

SOFL*

Start of Frame Low Register

0EH

SSR*

System Status Register

12H

TXCNTH

Transmit FIFO Byte-Count High Register

02H†

TXCNTL

Transmit FIFO Byte-Count Low Register

01H†

TXCON

USB Transmit FIFO Control Register

03H†

TXDAT

Transmit FIFO Data Register

00H†

TXFLG

Transmit FIFO Flag Register

04H†

TXSTAT

Endpoint Transmit Status Register

0CH†

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