USS820FD datasheet(44/56 Pages) AGERE

44 / 56 page

Agere Systems Inc.

Data Sheet, Rev. 1

August 2004

USB Device Controller

USS-820FD

Suspend and Resume Behavior

(continued)

Firmware Suspend Initiate (continued)

While the USS-820FD is suspended, its internal regis-

ters may still be read, presumably only in self-powered

devices. The interface timing for such reads is different

from register reads during operational mode, and is

specified in the Register Timing Characteristics

section. Register writes must not be attempted while

the USS-820FD is suspended, with the possible excep-

tion of the SCR.SRESET bit (see the SCR.SRESET

description for details). Certain register reads during

the nonsuspended state can cause USS-820FD device

the Register Reads with Side Effects section. These

820FD is suspended.

Hardware Resume Detect/Initiate

Wake-up can be initiated by either the host or the appli-

cation. A host-signaled wake-up (global resume) is

indicated when the host drives a K state on the USB

bus. A remote wake-up is initiated by the application by

asserting the USS-820FD RWUPN input pin. The USS-

820FD can also be awakened by firmware writing a 1

to SCR.SRESET if MCSR.FEAT = 1 (see

SCR.SRESET description for details). In these cases,

the USS-820FD will initiate a wake-up sequence as

described in the next section.

Hardware Resume Sequence

The USS-820FD starts a wake-up sequence by asyn-

chronously re-enabling its internal oscillator and PLL

and deasserting the SUSPN output pin. Once the inter-

nally generated clocks are stable (a period of 6 ms to

15 ms), then it enables clocks to the entire chip and

sets the SSR.RESUME register bit, which causes an

interrupt if SCRATCH.IE_RESUME register bit = 1. The

USS-820FD will require up to 15 ms to resume func-

tionality after a wake-up sequence is initiated. If the

wake-up was a remote wake-up, the USS-820FD will

then drive wake-up signaling (K) on the USB for 12 ms.

The USS-820FD requires a minimum of 7 ms from the

time a remote wake-up is initiated to the time it can

begin transmitting resume signaling upstream. This

guarantees adherence to the USB specification for

tWTRSM of 5 ms.

Firmware Resume Sequence

The USS-820FD indicates that the resume sequence is

complete by setting the SSR.RESUME register bit, and

possibly causing an interrupt. When firmware is

prepared for the application to return to normal opera-

tion, it must reset the SSR.RESUME register bit to

allow detection of any subsequent suspend events.

Special Suspend Considerations for Bus-

Powered Devices

In order to meet the USB current requirements while

suspended, care must be exercised to guarantee that

all board signals connected to the USS-820FD are at

their proper state. Voltages on USS-820FD input pins

must be guaranteed to be outside the switching

threshold region (i.e., either a valid CMOS logic 1 or 0).

Pins that are connected to external, powered-off

components must not be driven high.

If an external oscillator is used as the clock source for

the USS-820FD, it will most likely need to be turned off

by the USS-820FD SUSPN output pin in order to meet

the USB suspend current requirement. When the oscil-

lator is turned back on after a resume (when the

SUSPN pin deasserts) and is stabilizing (a period that

must not exceed tOSC as specified in Table 47), its

output clock must not have a frequency greater than

12 MHz. As a result, during this stabilization period, the

oscillator output must not provide more than

84,000 clocks.

The following list describes the expected (or required,

as noted) values on the USS-820FD pins for devices

which turn power off to external components during

suspend. Such devices must have SSR.SUSPPO = 1

to cause D[7:0], IRQN, and SOFN to be 3-stated during

suspend. They must also have MCSR.BDFEAT = 0

while suspended in order to guarantee that USBR and

DSA are 3-stated. These register settings avoid the

possibility of driving a logic 1 into a powered-off compo-

nent, which could result in excessive power consump-

tion and possible component damage.

External logic refers to components external to the

USS-820FD.

Note: Board signals which are connected to powered-

off components will most likely be naturally

pulled to logic 0 by the powered-off component.

■

A[4:0], IOCSN, RDN, WRN: Input-only pins. Their

value will be determined by external logic, and must

be a logic 0 or 1 to avoid current draw in the USS-

820FD.

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