USS820FD datasheet(21/56 Pages) AGERE

21 / 56 page

Agere Systems Inc.

Data Sheet, Rev. 1

August 2004

USB Device Controller

USS-820FD

Table 20. Endpoint Transmit Status Register (TXSTAT)—Address: 0CH; Default: 0000 0000B

This register contains the current endpoint status of the transmit FIFO specified by EPINDEX. This register is

endpoint indexed.

* For normal operation, this bit should not be modified by the user except as required by the implementation of USB standard commands, such

as SET_CONFIGURATION, SET_INTERFACE, and CLEAR_FEATURE [stall]. The SIE handles all sequence bit tracking required by normal

USB traffic, as documented in the USB specification, Section 8.6.

† Only writable if TXNAKE = 1.

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

TXSEQ

TXDSAM

TXNAKE

TXFLUSH

TXSOVW

TXVOID

TXERR

TXACK

R/W*

R/W

R/W†

Bit

Symbol

Function/Description

7TXSEQ

Transmitter Current Sequence Bit (Read, Conditional Write).* This bit is trans-

mitted in the next PID and toggled on a valid ACK handshake. This bit is toggled by

hardware on a valid SETUP token. This bit can be written by firmware if the TXSOVW

bit is set when written together with the next TXSEQ value.

6TXDSAM

Transmit Data-Set-Available Mode. If set, a NAK response to an IN token causes

the corresponding RXAV/TXAV bit in the DSAV register to set, and the DSA output pin

to assert (if enabled by MCSR.BDFEAT), rather than the standard condition (transmit

data set empty). This only occurs on NAKs caused by TXFIF = 00. This bit must not

be set for isochronous endpoints. When reset to 0 (along with MCSR.FEAT,

MCSR.BDFEAT, and TXSTAT.TXNAKE), the device will behave like revision B.

5TXNAKE

Transmit NAK Mode Enable. If set, a NAK response to an IN token causes the

TXVOID bit and the corresponding bits in the SBI/SBI1 register to set, causing an

IRQN interrupt (if enabled). This only occurs on NAKs caused by TXFIF = 00. This bit

must not be set for isochronous endpoints. When set this bit also changes the

meaning and usage of the TXSTAT.TXVOID bit. When reset to 0 (along with

MCSR.FEAT, MCSR.BDFEAT, and TXSTAT.TXDSAM), the device will behave like

revision B.

4TXFLUSH Transmit FIFO Packet Flushed (Read Only). Updated at each SOF. When set, this

bit indicates that hardware flushed a stale isochronous data packet from the transmit

FIFO at SOF.

Behavior when MCSR.FEAT = 0:

To guard against a missed IN token in isochronous mode, if, with TXFIF[1:0] = 11,

no IN token is received for the current endpoint, hardware automatically flushes

the oldest packet and decrements the TXFIF[1:0] value. This flush does not occur

if there is only one data set present (TXFIF = 01/10).

Behavior when MCSR.FEAT = 1:

A firmware data set write causes a TXFIF bit to set. For isochronous endpoints,

this data set does not become visible to the host until the next SOF. The data set is

intended to be read out during that frame. If that read does not occur (possibly due

to a lost IN packet), that data set is flushed at the next SOF, setting TXFLUSH. If

firmware writes two data sets during a single frame (TXFIF must have equalled 00

at the start of that frame), the first, older data set written is flushed at the subse-

quent SOF, setting TXFLUSH.

USS820FD Datasheet(PDF) 21 Page - Agere Systems

USS820FD Datasheet(HTML) 21 Page - Agere Systems

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56

Datasheet Download

Link URL