LM94 datasheet(5/24 Pages) NSC

5 / 24 page

9.0 Pin Descriptions

Symbol

Pin #

Type

Function

GPIO_0/TACH1

Digital I/O

(Open-Drain)

Can be configured as fan tach input or a general purpose

open-drain digital I/O.

GPIO_1/TACH2

Digital I/O

(Open-Drain)

Can be configured as fan tach input or a general purpose

open-drain digital I/O.

GPIO_2/TACH3

Digital I/O

(Open-Drain)

Can be configured as fan tach input or a general purpose

open-drain digital I/O.

GPIO_3/TACH4

Digital I/O

(Open-Drain)

Can be configured as fan tach input or a general purpose

open-drain digital I/O..

GPIO_4 /

P1_THERMTRIP

Digital I/O

(Open-Drain)

A general purpose open-drain digital I/O. Can be configured to

monitor a CPU’s THERMTRIP signal to mask other errors. Supports

TTL input logic levels and AGTL compatible input logic levels.

GPIO_5 /

P2_THERMTRIP

Digital I/O

(Open-Drain)

A general purpose open-drain digital I/O. Can be configured to

monitor a CPU’s THERMTRIP signal to mask other errors. Supports

TTL input logic levels and AGTL compatible input logic levels.

GPIO_6

Digital I/O

(Open-Drain)

Can be used to detect the state of CPU1 IERR or a general purpose

open-drain digital I/O. Supports TTL input logic levels and AGTL

compatible input logic levels.

GPIO_7

Digital I/O

(Open-Drain)

Can be used to detect the state of CPU2 IERR or a general purpose

open-drain digital I/O. Supports TTL input logic levels and AGTL

compatible input logic levels.

VRD1_HOT

Digital Input

CPU1 voltage regulator HOT. Supports TTL input logic levels and

AGTL compatible input logic levels.

VRD2_HOT

Digital Input

CPU2 voltage regulator HOT. Supports TTL input logic levels and

AGTL compatible input logic levels.

P2_VID6/GPI8

Digital Input

CPU2 VID6 input. Could also be used as a general purpose input to

trigger an error event. Supports TTL input logic levels and AGTL

compatible input logic levels.

P1_VID6/GPI9

Digital Input

CPU1 VID6 input. Could also be used as a general purpose input to

trigger an error event. Supports TTL input logic levels and AGTL

compatible input logic levels.

SMBDAT

Digital I/O

(Open-Drain)

Bidirectional System Management Bus Data. Output configured as

5V tolerant open-drain. SMBus 2.0 compliant.

SMBCLK

Digital Input

System Management Bus Clock. Driven by an open-drain output,

and is 5V tolerant. SMBus 2.0 Compliant.

ALERT/XtestOut

Digital Output

(Open-Drain)

Open-drain ALERT output used in an interrupt driven system to

signal that an error event has occurred. Masked error events do not

activate the ALERT output. When in XOR tree test mode, functions

as XOR Tree output.

RESET

Digital I/O

(Open-Drain)

Open-drain reset output when power is first applied to the LM94.

Used as a reset for devices powered by 3.3V stand-by. After reset,

this pin becomes a reset input. If this pin is not used, connection to

an external resistive pull-up is required to prevent LM94 malfunction.

AGND

GROUND Input

Analog Ground. Digital ground and analog ground need to be tied

together at the chip then both taken to a low noise system ground.

A voltage difference between analog and digital ground may cause

erroneous results.

REF

Analog Output

2.5V used for external ADC reference, or as a V

REF reference

voltage

LM94 Datasheet(PDF) 5 Page - National Semiconductor (TI)

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