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LM94 Datasheet(PDF) 7 Page - National Semiconductor (TI) |
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LM94 Datasheet(HTML) 7 Page - National Semiconductor (TI) |
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7 / 24 page ![]() 9.0 Pin Descriptions (Continued) Symbol Pin # Type Function AD_IN11 33 Analog Input (SCSI_Core) Analog input for +2.5V monitoring, nominal 3⁄4 scale reading. This pin may also be used to monitor an analog temperature sensor such as the LM60, since readings from this input can be routed to the fan control logic. AD_IN12 34 Analog Input (Mem_Core) Analog input for +1.969V monitoring, nominal 3⁄4 scale reading. AD_IN13 35 Analog Input (Mem_Vtt) Analog input for +0.984V monitoring, nominal 3⁄4 scale reading. AD_IN14 36 Analog Input (Gbit_Core) Analog input for +0.984V S/B monitoring, nominal 3⁄4 scale reading. AD_IN15 37 Analog Input (-12V) Analog input for -12V monitoring. External resistors required to scale to positive level. Full scale reading at 1.236V, , nominal 3⁄4 scale reading. This pin may also be used to monitor an analog temperature sensor such as the LM60, since readings from this input can be routed to the fan control logic. Address Select 38 3 level analog input This input selects the lower two bits of the LM94 SMBus slave address. 3.3V SB (AD_IN16) 39 POWER (V DD) +3.3V standby power V DD power input for LM94. Generally this is connected to +3.3V standby power. The LM94 can be powered by +3.3V if monitoring in low power states is not required, but power should be applied to this input before any other pins. This pin also serves as the analog input to monitor the 3.3V stand-by (SB) voltage. It is necessary to bypass this pin with a 0.1 µF in parallel with 100 pF. A bulk capacitance of 10 µF should be in the near vicinity. The 100 pF should be closest to the power pin. GND 40 GROUND Digital Ground. Digital ground and analog ground need to be tied together at the chip then both taken to a low noise system ground. A voltage difference between analog and digital ground may cause erroneous results. PWM1 41 Digital Output (Open-Drain) Fan control output 1. PWM2 42 Digital Output (Open-Drain) Fan control output 2 P1_VID0/P1_VID7 43 Digital Input Voltage Identification signal from the processor. Supports TTL input logic levels and AGTL compatible input logic levels. P1_VID1 44 Digital Input Voltage Identification signal from the processor. Supports TTL input logic levels and AGTL compatible input logic levels. P1_VID2 45 Digital Input Voltage Identification signal from the processor. Supports TTL input logic levels and AGTL compatible input logic levels. P1_VID3 46 Digital Input Voltage Identification signal from the processor. Supports TTL input logic levels and AGTL compatible input logic levels. P1_VID4 47 Digital Input Voltage Identification signal from the processor. Supports TTL input logic levels and AGTL compatible input logic levels. P1_VID5 48 Digital Input Voltage Identification signal from the processor. Supports TTL input logic levels and AGTL compatible input logic levels. P1_PROCHOT 49 Digital I/O (Open-Drain) Connected to CPU1 PROCHOT (processor hot) signal through a bidirectional level shifter. Supports TTL input logic levels and AGTL compatible input logic levels. P2_PROCHOT 50 Digital I/O (Open-Drain) Connected to CPU2 PROCHOT (processor hot) signal through a bidirectional level shifter. Supports TTL input logic levels and AGTL compatible input logic levels. www.national.com 7 |
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