M166 datasheet(21/127 Pages) SIEMENS

21 / 127 page

30Mar98@15:00h

Semiconductor Group

Version 1.2, 12.97

C166 Family Instruction Set

Instruction Opcodes

The following pages list the instructions of the 16-bit microcontrollers ordered by their hexadecimal

opcodes. This helps to identify specific instructions when reading executable code, ie. during the

debugging phase.

Notes for Opcode Lists

These instructions are encoded by means of additional bits in the operand field of the

instruction

x0H – x7H:

Rw, #data3

Rb, #data3

x8H – xBH:

Rw, [Rw]

Rb, [Rw]

xCH – xFH:

Rw, [Rw +]

Rb, [Rw +]

For these instructions only the lowest four GPRs, R0 to R3, can be used as indirect address

pointers.

These instructions are encoded by means of additional bits in the operand field of the

instruction

00xx.xxxxB:

EXTS

ATOMIC

01xx.xxxxB:

EXTP

10xx.xxxxB:

EXTSR

EXTR

11xx.xxxxB:

EXTPR

The ATOMIC and EXTended instructions are not available in the SAB 8XC166(W) devices.

Notes on the JMPR Instructions

The condition code to be tested for the JMPR instructions is specified by the opcode.

Two mnemonic representation alternatives exist for some of the condition codes.

Notes on the BCLR and BSET Instructions

The position of the bit to be set or to be cleared is specified by the opcode. The operand

‘bitoff.n’ (n = 0 to 15) refers to a particular bit within a bit-addressable word.

Notes on the Undefined Opcodes

A hardware trap occurs when one of the undefined opcodes signified by ‘----’ is decoded by

the CPU.

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