L9788 datasheet(30/264 Pages) STMICROELECTRONICS

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Operation behavior

L9788

30/264

DS12308 Rev 4

3.1.5

Power up from WK_IN

The chip is powered up if WK_IN signal has a rising edge and stays asserted for WK_Tfilter.

In case the power up of the chip is not completed in a MRD_EN_TIMEOUT from WK_IN

rising edge detection the Main Relay Driver is switched off and the chip goes in OFF state.

The u-chip will not power up until further rising edge on WK_IN pin. This detection of a

WK_IN condition flag is named WK_IN_DET (detection of a WK_IN condition) and is

cleared by VDD5/VDDIO under voltage or by the MSC command WK_IN_RST. In these

cases, if no other power-on source is active, a power down sequence is started.When U

chip is already in on state (the logic is out of power on reset), the rising edge on pin WK_IN

only sets a flag, with no impact on power supply.

The Main Relay Driver is not switched on by WAKE_IN_DET rising edge if the device is in

permanent battery. To recognize the permanent battery condition the main logic has to be

out of Power On Reset within Tbattery_det.

There is a MSC bit (WAKE_IN_PIN_FLT in read command 15 frame 2) to indicate the status

of WK_IN pin signal after filter time.

A negative glitch on WK_IN can produce unwanted power up and also prevent the correct

power down.

To cover the major cases the falling edge filtering is done both in the VB_STBY domain and

in the VB_IN domain. Depending on which supply is present the behavior is described in the

following cases:

If VB_STBY is present the falling edge filtering is applied also to power up so a

negative glitch on WK_IN will not power up the device.

If VB_STBY is not present a negative glitch on WK_IN will power up the device.

If VB_IN is present (after the device is already powered up) the falling edge filtering on

WK_IN avoids that a glitch (happening in PHOLD after the MSC has cleared the

WK_IN detection) is recognized as valid detection and the device is kept on.

3.1.6

Power down from WK_IN when PHOLD=0

The chip is powered down if the MSC clears, by the MSC command WK_IN_RST, the

detection of WK_IN positive edge if no other power up source is active. The power down is

actuated even if WK_IN is still high. The power down is not activated by WK_IN going low or

WK_IN low level. The detection reset by MSC command, WK_IN_RST

(CONFIG_REG12[7]), is active at level, so from when MSC writes them at 1 they keep on

clearing the detections. If there is further wake detection signal, the detection signal will be

cleared, until the MSC writes 0 in the bits.

Condition:

4.8 V ≤ VB_IN ≤ 18 V, Tj -40 to 175 °C unless otherwise specified.

Table 10. WK pins electrical characteristics

Symbol

Parameter

Test condition

Min

Typ

Max

Unit

VIH

Logic input high

voltage threshold

3.6

4.1

WK_IN

VIL

Logic input low

voltage threshold

3.1

3.6

WK_IN

VIHYS

Logic input hysteresis -

0.1

0.8

WK_IN

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