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L9788 Datasheet(PDF) 41 Page - STMicroelectronics |
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L9788 Datasheet(HTML) 41 Page - STMicroelectronics |
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41 / 264 page  3.3 Reset strategies Figure 13. Reset table Note: When VB_STBY_UV happens, it stops the EOT counter.The EOT counter will resume when vb_stby_uv goes low (no undervoltage). IN x no rese t xx -- xx *1 5 xx x x -- - - - - - x - --- -- - - - - -- - x - - - - - -- - - - - - - - - - - - - x - - - - - - - - - - - - - - - - x --- x -- - - - - - - - - x- - - -- - - - - - - - - - - - - - - -- - - --- -- - -- - - - - - - - - - - - - - - - -x x - *1 1 *1 1 *1 6 -- - - - - - - - - - - - *9 *9 *9 *9 *9 *8 *8 *9 *8 *9 *1 3 *1 3 *1 3 *1 3 *1 3 *1 2 *1 3 *1 3 *1 2 *1 0 *1 0 *1 2 *1 0 *1 2 x - WDA GADG2511160811PS At the rising edge of reset, the MSC communication is reset. un-sent up stream frame should be discard. RLY4 and STR[2:3] are MSC configured as starters (CONFIG3[0]=CONFIG3[4:5]=1) LIN works as receiving mode only (if the disable of the transmitting mode is enabled by MSC) LIN works as receiving mode only due to watchdog BOSCH IP the WDA_ERR_CNT can be reset if also RST_PRL is activated CAN works as receiving-only mode only if bit CAN_TDI =1 If the related delay off function is active the driver stays ON CAN works as Low-power mode CAN works as receiving-only mode RLY4 and STR[2:3] are stop by EN_N/EN_P if they are configured or not as starter When VDD5_OFF_SEL=1, VDD5 does not depend on VB_IN UV. If VDD5_OFF_SEL=0, VDD5 depends on VB_IN UV excluded WAKE_UP_TIMER_START_STOP, EOT_MODE, CAN parameters, WAKE_UP_TIMER_EN_SEL, KEY_OC_RERTY_MAX_EN *16 *15 *14 *13 *12 *11 *10 *9 *8 *7 *6 *5 OT_DET/WAKE_UP_CAN_DET WAKE_IN_DET/WAKE_UP_E POWER HOLD KEY_IN_DET wake_up_timer(EOT) TRACK 5V VDD5 V3V3 WDA_REG_RST WDA_CNT_RST RST_PRL WDA diagnostic register WDA config register WDA question register WDA reset counter WDA power down counter WDA error counter WDA sequence WDA (OUT) TRACK(5V) VDD5(5V) VCP BUCK BOOST V3V3A V3V3D CAN VRS K/LIN IGN[1:6] PRD[1:5] DELAY OFF FUNCTION RLY4 STR[2:3] *7 HSD/LSD[1:2:3] LED[1:2] RLY[1:5] SOL[1:2] O2H[1:2] INJ[1:4] MRD FAULT WARNING RSTC (OUT) RSTN (OUT) pull down time RSTN (OUT) FIN_WAKE MSC REGISTERS*14 MSC_ACT MSC communication*5 (default enabled ) afterrun reset enable bit (TNL) MSC Td_UV_RST active stop/reset partial functionality not active normal operation detection VB_STBY FLAG READ BY MSC Td_UV_RST Td_UV_RST Td_UV_RST Td_UV_RST Td_UV_RST Td_UV_RST TWDA_RST TNL_RST INC+1 SUPPLY DOMAIN UV VB_STBY WAKE_UP_CAN WAKE_UP_EOT VB_STBY EVENT VB_IN_OV_RST_EN MSC en/dis (for BUCK, VDD5, TRK) t>tTBOV2 OV VB_IN/VB_IN_SW tTBOV1<t<tTBOV2 OV UV V3V3 V3V3A V3V3D OV UV BUCK 6V VPRE OV UV MSC en/dis OV UV REG 5V VDD5 UV VDDIO FAULT OSC LOSS GND BID PIN WDA(IN) ERR_CNT>4 wda_init=1 MSC ERR_CNT>7 MSC en/dis KEY_IN=0 and PWR_CNT>7 WDA_QA V3V3D MSC_ACT SW_RESET en/dis MSC active reset afterrun TRACK 5V WARNING FAULT EN_N EN_P RSTN (IN) BID PIN IN OV/UV internal reset WATCHDOG SEO_OUT is triggered by KEY_IN=0 |
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