9.2.3 24-Bit, 200 kSPS, Delta-Sigma ADS127L11 ADC Driver Circuit With FDA Noise Filter

The application circuit in Figure 9-9 shows an schematic for a 24-bit-precision, 200-kSPS, delta-sigma, ADC.

The circuit is used to measure the driving capacity of the INA851 with the ADS127L11 ADC.

The ADS127L11 ADC offers two digital filters to optimize for ac applications (wideband filter) or dc applications

(Sinc4 filter). Application Curves shows measurement results in both filter settings. For detailed design

procedure to operate the ADS127L11 ADC, see the ADS127L11EVM-PDK evaluation module.

+

–

RG

VS+

OUT+

VS

IN

IN+

RG+

OUT

VOCM

RF

RF

R1

R2

R4

R3

G02

G02+

3 k

5 k

5 k

3 k

5 k

1.25 k

R5

R6

5 k

1.25 k

LDO

LDO

VCLAMP+

VCLAMP

RG

ADS127L11

INP

INN

FDA_IN

FDA_IN+

+

–

–

+

INA851

15 V

15 V

2.5 V

4

3

2

1

16

15

14

13

7

5

6

9

10

11

12

OVP

OVP

+

–

AVDD

AVSS

VIN+

VIN-

10

150 pF

CFB

CFB

RFIL

RFIL

CCM

CCM

VREF

5.2 V

ADS127L11 V

VCM Pin

2x Input Range

CDIFF

47.4

47.4

51 pF

51 pF

510 pF

100 pF

100 pF

Figure 9-9. Driving the Delta-Sigma ADC ADS127L11

9.2.3.1 Design Requirements

The design requirements for the application driving the ADS127L11 ADC are listed in the following table.

Table 9-3. Design Parameters

PARAMETER

VALUE

Differential-to-differential conversion

VINDIFF to VOUTDIFF

Supply voltages

VS± = ±15 V, AVDD = 5.2 V, VREF = 2.5 V

Full-scale range of ADC for FSR

FSR = ± 5 V

Data rate of ADC

fDATA = 187.5 kSPS

ADC filter configuration

(1) High-speed mode, Sinc4 filter, OSR = 64

(2) High-speed mode, wideband filter, OSR = 64

INA gain and filter configuration

See Table 9-4 and Table 9-5

Signal frequency

fIN = 1 kHz

RC kickback filter(1)

RFIL = 47.4 Ω + CDIFF = 510 pF + RFIL = 47.4 Ω, CFIL = 51 pF

(1)

A trade-off must be considered between THD, frequency response and drift. The differential current drift into the ADC can interact with

this filter resistors and result in higher drift errors. However, low resistance degrades the phase margin of the INA851. For low drift

applications, keep RFIL < 50 Ω.

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INA851

SBOS999A – MARCH 2022 – REVISED OCTOBER 2022

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