XE161FL datasheet(41/107 Pages) INFINEON

41 / 107 page

XE161FL, XE161HL

XE166 Family / Econo Line

Functional Description

Data Sheet

V1.2, 2012-07

With its maximum resolution of 2 system clock cycles, the GPT2 module provides

precise event control and time measurement. It includes two timers (T5, T6) and a

capture/reload register (CAPREL). Both timers can be clocked with an input clock which

is derived from the CPU clock via a programmable prescaler or with external signals. The

counting direction (up/down) for each timer can be programmed by software or altered

dynamically with an external signal on a port pin (TxEUD). Concatenation of the timers

is supported with the output toggle latch (T6OTL) of timer T6, which changes its state on

each timer overflow/underflow.

The state of this latch may be used to clock timer T5, and/or it may be output on pin

T6OUT. The overflows/underflows of timer T6 can also be used to clock the CAPCOM2

timers and to initiate a reload from the CAPREL register.

The CAPREL register can capture the contents of timer T5 based on an external signal

transition on the corresponding port pin (CAPIN); timer T5 may optionally be cleared

after the capture procedure. This allows the XE161xL to measure absolute time

differences or to perform pulse multiplication without software overhead.

The capture trigger (timer T5 to CAPREL) can also be generated upon transitions of

GPT1 timer T3 inputs T3IN and/or T3EUD. This is especially advantageous when T3

operates in Incremental Interface Mode.

XE161FL Datasheet(PDF) 41 Page - Infineon Technologies AG