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XE161FL Datasheet(PDF) 13 Page - Infineon Technologies AG |
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XE161FL Datasheet(HTML) 13 Page - Infineon Technologies AG |
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13 / 107 page ![]() XE161FL, XE161HL XE166 Family / Econo Line General Device Information Data Sheet 9 V1.2, 2012-07 Key to Pin Definitions • Ctrl.: The output signal for a port pin is selected by bit field PC in the associated register Px_IOCRy. Output O0 is selected by setting the respective bit field PC to 1x00 B, output O1 is selected by 1x01B, etc. Output signal OH is controlled by hardware. • Type: Indicates the pad type and its power supply domain (B, M). – St: Standard pad – Sp: Special pad e.g. XTALx – DA: Digital IO and analog input – In: Input only pad – PS: Power supply pad Table 6 Pin Definitions and Functions Pin Symbol Ctrl. Type Function 1 TESTM IIn/B Testmode Enable Enables factory test modes, must be held HIGH for normal operation (connect to V DDPB). An internal pullup device will hold this pin high when nothing is driving it. 2TRST IIn/B Test-System Reset Input For normal system operation, pin TRST should be held low. A high level at this pin at the rising edge of PORST activates the XE161xL’s debug system. In this case, pin TRST must be driven low once to reset the debug system. An internal pulldown device will hold this pin low when nothing is driving it. 3 P6.3 O0 / I St/B Bit 3 of Port 6, General Purpose Input/Output CCU63_COU T62 O1 St/B CCU63 Channel 2 Output T3OUT O2 St/B GPT12E Timer T3 Toggle Latch Output U1C1_SELO 0 O3 St/B USIC1 Channel 1 Select/Control 0 Output U1C1_DX2D I St/B USIC1 Channel 1 Shift Control Input ADC0_REQT RyF ISt/B External Request Trigger Input for ADC0/1 |
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