TC9293F/FN/N

2003-06-27

4

Description of Block Operation

1. Crystal Oscillation Circuit and Timing Generator

Clock required for internal operation can be generated when crystal and capacitors are connected as

shown in the following figure.

Further, this converter is also operable when system clock is input from the outside through XI pin (pin

15).

However, a through consideration is required in this case because noise distortion and S/N ratio of the

DA converter are largely affected by qualities of wave form such as jitter, rising and falling characteristics,

etc. of system clock.

CL = 10~33 pF

Use a crystal having a low CI value and good statability.

The timing generator generates clock required for the digital filter, de-emphasis filter, interpolation filter

and process timing signal.

2. Data Input Circuit

DATA and LRCK are taken in the shift register in the LSI at the rising edge of BCK.

As shown in the following timing example, it is therefore necessary to input DATA and LRCK in

synchronism with the falling edge of BCK.

Further, because DATA has been to designed that 16 bits before the change point of LRCK are made

effective data.

Figure 1 Configuration of Crystal Oscillation Circuit.

Figure 2a Example of Input Timing Diagram ( R

L/

==== “L”)