IP1201 datasheet(14/29 Pages) IRF

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iP1201

Mode of Operation

The iP1201 can be configured to provide either two

independent dual outputs or single paralleled out-

put with current share. In dual output mode, the two

error amplifiers of the PWM controller operate inde-

pendently. Each output voltage of the iP1201 block

is controlled by its own error amplifier. The output of

the error amplifier and the internally generated ramp

signal are compared to produce PWM pulses of fixed

frequency that drive the internal power switches. In

this mode, the VP-ref pin must be connected to Vref

pin. Vref pin is the internally generated 0.8V refer-

ence input of first error amplifier . Refer to the inter-

nal block diagram of the iP1201 in Fig.1.

In single output mode, one error amplifier controls

the output voltage and the other amplifier monitors

the inductor current information for current sharing.

In this mode, VP-ref pin must be disconnected from

Vref pin and connected to the output of the inductor.

See Fig. 16. The inductor current information is pro-

vided through external shunts placed in series with

the output inductors.

A lossless inductor current sensing scheme can

also be implemented as shown in Fig. 17 where

the current is sensed throughthe DC resistance of

the inductor.

The iP1201 can also be configured in dual output

tracking mode where the second output tracks the

first output.

For a specific output configuration, follow the con-

nection diagram shown in Fig.16, Fig.17 and Fig.18

at the end of this section.

Out of Phase Operation

The dual output PWM controller inside the iP1201

provides a 180° out of phase operation of the PWM

outputs. This method of control offers the advan-

tage of reducing the amount of input bypass ca-

pacitors due to increase in input ripple frequency

and hence reduction of ripple amplitude. Moreover,

for paralleled output configurations 180° phase

shifting contributes to smaller output capacitors due

to output inductor ripple current cancellation and

ripple reduction.

Frequency and Synchronization

The operating switching frequency (f

SW) range of

iP1201 is 200 kHz to 400 kHz. The desired frequency

is set by placing an external resistor to the RT pin of

the iP1201. See Fig. 11 for the proper resistor value.

The iP1201 is capable of accepting an external digi-

tal synchronization signal. Synchronization will be

enabled by the rising edge clock. The free running

oscillator frequency is twice the per-channel fre-

quency. During synchronization, RT is selected such

that the free running frequency is 20% below the

synchronization frequency. The maximum synchro-

nization frequency that iP1201 can accept is 800kHz.

Note that the actual free running frequency of indi-

vidual output is half the synchronization frequency.

Synchronization capability is provided both in inde-

pendent and parallel configurations. When unused,

the SYNC pin must be left floating.

Overcurrent Protection/Autorestart

The Overcurrent Protection function of the iP1201

offers two distinct modes: HICCUP of the output

and Overcurrent Shutdown. If the Hiccup pin is

pulled high (Hiccup enabled), hiccup mode will be

selected. If Hiccup pin is pulled low (Hiccup dis-

abled), overcurrent shutdown will be selected.

During overloads, in HICCUP disabled mode, the

controller shuts down as soon as the trip threshold

is reached. In HICCUP enabled mode, when

overcurrent trip threshold is reached, the power

supply output shuts down and attempts to restart.

The time duration between the shutdown of the

output and the restart is determined by the time it

takes to discharge the soft start capacitor. Typically,

the discharge time of the soft start capacitor is 10

times the charge time. The duty cycle of the hiccup

process is typically 5%.The output will stay in hic-

cup indefinitely until the overload is removed. The

typical overcurrent trip threshold of the device is

internally set at 20A.

Overvoltage Protection (OVP)

Overvoltage is sensed through separate output volt-

age sense pins FB1s and FB2s. A separate OVP

circuit is provided for each output and the OVP

threshold is set to 115% of the output voltage. Upon

overvoltage condition of either one of the outputs,

the OVP forces a latched shutdown on both out-

puts. In this mode, the upper FETs turn off and the

lower FETs turn on, thus crowbaring the outputs.

Reset is performed by recycling the ENABLE pin.

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