IP1201 datasheet(17/29 Pages) IRF

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iP1201

Only a few external components are required to com-

plete a dual output synchronous buck power supply

using iP1201. The following procedure will guide

the designer through the design and selection pro-

cess of these external components.

A typical application for iP1201 will be:

IN = 3.3V, VOUT1 = 1.5V, IOUT1 = 10A, VOUT2 = 2.5V, IOUT2 =

6A, f

sw = 200kHz, Vp-p1 = Vp-p2 = 40mV

Setting the Output Voltage

The output voltage of the iP1201 is set by the 0.8V

reference Vref and external voltage dividers.

Fig. 19: Typical scheme for output voltage setting

OUT1 is set according to equation (1):

OUT1 = Vref x (1 + R9 /R7 ) (see Fig. 19)

(1)

Setting R

7 to 1K, VOUT1 to 1.5V and Vref to 0.8V, will

result in R

9= 875 ohms (select 887 ohms).

Final

values can be selected according to the desired

accuracy of the output.

If the 0.8V reference is used to set the voltage for the

second output V

OUT2, VP-ref pin must be shorted to

Vref pin and in a similar way, voltage divider resis-

tors are selected for the second output V

OUT2. The

second output can also be set by applying an exter-

iP1201 Design Procedure

R13

R14

iP1201

C26

(Optional)

Vout1

FB1

FB1S

nal reference source to VP-ref. In this case, to en-

sure proper start-up, power to VP-ref and iP1201

must be applied simultaneuosly.

Setting the Overvoltage Trip

Both outputs of the iP1201 will shut down if either

one of the outputs experiences a voltage in the range

of 115% of V

OUT. The overvoltage sense pins FB1s

and FB2s are connected to the output through volt-

age dividers, R

13 and R14 (Fig. 19), and the trip

setpoints are programmed according to equation

(1). Separate overvoltage sense pins FB1

s and FB2s

are provided to protect the power supply output if for

some reason the main feedback loop is lost (for

instance, loss of feedback resistors). If this redun-

dancy is not required and if Type II control loop com-

pensation scheme is utilized, FB1s and FB2s pins

can be connected to FB1 and FB2 pins respectively.

An optional 100pF capacitor (C26) is used for delay

and filtering purposes.

Setting the Soft-Start Capacitor

The soft start capacitor C

ss is selected according to

equation (2):

ss = 40 x Css

(2)

where,

ss is the output voltage ramp time in milliseconds,

and C

ss is the soft start capacitor in µF.

A 0.1µF capacitor will provide an output voltage ramp-

up time of about 4ms.

Input Capacitor Selection

The switching currents impose RMS current require-

ments on the input capacitors. The expression in

equation (3) allows the selection of the input ca-

pacitors:

(3)

where,

D is the duty cycle and is expressed as:

D = V

OUT / VIN.

For output1 of the above example D= 0.45 and,

RMS = 10 x SQRT (0.45(1-0.45)) = 5A

For output2 of the above example D = 0.75 and,

)

(

LOAD

RMS

−

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