AP62300/AP62301/AP62300T

Document number: DS41958 Rev. 3 - 2

14 of 23

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January 2021

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AP62300/AP62301/AP62300T

Application Information (continued)

3

Enable (continued)

Alternatively, a small ceramic capacitor can be added from EN to GND. When EN is not driven externally, this capacitor increases the time needed

for the EN pin voltage to reach its logic high threshold, which delays the startup of the output voltage. This is useful when sequencing multiple

power rails to minimize input inrush current. When the EN pin voltage starts from 0V, the amount of capacitance for a given delay time is

approximated by:

������������[������������] ≈ ������. ������������������ ∙ ������������[������������]

Eq. 3

Where:



Cd is the time delay capacitance in nF



td is the delay time in ms

4

Electromagnetic Interference (EMI) Reduction with Ringing-Free Switching Node

In some applications, the system must meet EMI standards. In relation to high frequency radiation EMI noise,

the switching node’s (SW’s) ringing

amplitude is especially critical. To dampen high frequency radiated EMI noise, the AP62300/AP62301/AP62300T device implements a proprietary,

multi-level gate driver scheme that achieves a ringing-free switching node without sacrificing the switching nod

e’s rise and fall slew rates as well

as

the converter’s power efficiency.

5

Adjusting Undervoltage Lockout (UVLO)

Undervoltage lockout is implemented to prevent the IC from insufficient input voltages. The AP62300/AP62301/AP62300T device has a UVLO

comparator that monitors the input voltage and the internal bandgap reference. The AP62300/AP62301/AP62300T disables if the input voltage

falls below 3.6V. In this UVLO event, both the high-side and low-side power MOSFETs turn off.

Some applications may desire higher VIN UVLO threshold voltages than is provided by the default setup. A 5.5µA hysteresis pull-up current

source on the EN pin along with an external resistive divider (R3 and R4) configures the VIN UVLO threshold voltages as shown in Figure 39.

VIN

R3

R4

ON

EN

1.2V

I1

1.5μA

I2

5.5μA

20kΩ

+

–

Figure 39. Programming UVLO

The resistive divider resistor values are calculated by:

������������ =

������. ������������������ ∙ ������������������ − ������������������������

������. ������������������������������

Eq. 4

������������ =

������. ������ ∙ ������������

������������������������ − ������. ������������ + ������������������ ∙ ������������

Eq. 5

Where:



VON is the rising edge VIN voltage to enable the regulator and is greater than 4.15V



VOFF is the falling edge VIN voltage to disable the regulator and is greater than 3.85V