LTM8063 datasheet(20/28 Pages) AD

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LTM8080

Rev. 0

For more information www.analog.com

VOUT Fast Start-Up

For ultralow noise applications that require low 1/f

noise (i.e., at frequencies below 100Hz), a larger value

SET pin capacitor is required, up to 22µF. While this

would typically significantly increase the regulator’s

start-up time, the LTM8080 incorporates fast start-up

circuitry that increases the SET pin current to about 2mA

during start-up.

A 2mA current source remains engaged to charge the SET

pin while the respective PGFB is below 300mV unless the

regulator is in current limit, dropout, thermal shutdown,

or input voltage is below minimum VIN.

If fast start-up capability is not used, tie PGFBn to VBUS or

VOUT for output voltages above 300mV. Note that doing

so also disables power good functionality.

Programmable Power Good

Power good threshold is user-programmable using the

ratio of two external resistors, RPG1,3 and RPG2,4 (refer

to Block Diagram and Equation 3).

VOUT(PG_THRESHOLD) =

0.3V •

RPG1,3

RPG2,4

− IPGFB•RPG1,3

(3)

If the PGFB pin increases above 300mV, the respective

open-collector PG pin de-asserts and becomes high

impedance. The power good comparator has 7mV hys-

teresis and 5µs of deglitching. Therefore, the PGFB pin

current (IPGFB = 25nA, typically) must be considered

when determining the resistor divider network. The PGFB

pin current (IPGFB) can be ignored if RPG2,4 is less than

30k. If power good functionality is not used, float the

PG pin. Please note that programmable power good and

fast start-up capabilities are disabled for output voltages

below 300mV.

PCB Layout

Most of the headaches associated with PCB layout have

been alleviated or even eliminated by the high level of

integration of the LTM8080. The LTM8080 is, neverthe-

less, a switching power supply, and care must be taken to

minimize EMI and ensure proper operation. Even with a

high level of integration, you may fail to achieve specified

operations with a haphazard or poor layout. See Figure 2

for a suggested layout. Ensure that the grounding and

heat sinking are acceptable.

A few rules to keep in mind are:

1. Place CSET, RSET, COUT, CBUS, and RT as close to their

respective pins.

2. Place the CIN capacitor as close as possible to the VIN

and GND connection of the LTM8080.

3. Place the COUT capacitor as close as possible to the

VOUT and GND connection of the LTM8080.

4. Place the CIN and CBUS capacitors so that their ground

current flows directly adjacent to or underneath the

LTM8080.

5. Connect all the GND connections to as large a copper

pour or plane area as possible on the top layer. Avoid

breaking the ground connection between the external

components and the LTM8080.

6. Use vias to connect the GND copper area to the

board’s internal ground planes. Liberally distribute

these GND vias to provide both a good ground con-

nection and thermal path to the internal planes of the

printed circuit board. Pay attention to the location and

density of the thermal vias as shown in Figure 2. The

LTM8080 can benefit from the heat sinking afforded

by vias that connect to internal GND planes at these

locations due to their proximity to internal power han-

dling components. The optimum number of thermal

vias depends upon the printed circuit board design.

For example, a board might use tiny holes. Therefore,

it should employ more thermal vias than a board that

uses larger holes.

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