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AD74115BCPZ Datasheet(PDF) 12 Page - Analog Devices |
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AD74115BCPZ Datasheet(HTML) 12 Page - Analog Devices |
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12 / 103 page ![]() Data Sheet AD74115 SPECIFICATIONS analog.com Rev. 0 | 12 of 103 Table 11. Digital Outputs (Sourcing and Sinking) (Continued) Parameter Min Typ Max Unit Test Conditions/Comments Propagation Delay1 From the SYNC rising or the GPIO edge (whichever is in use) to a 0.5 V transition on the I/OP screw terminal Propagation High Time, tPH, and Propagation Low Time, tPL, Internal FETs 4 μs tPH and tPL, External FETs 7 μs FET CISS < 1 nF Transition Time1 10% to 90% of the transition on the I/OP screw terminal Rise, tR, and Fall, tF, Internal FETs 2 μs tR and tF External FETs 5 μs 1 Guaranteed by design and characterization. |
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