SE050B2 datasheet(12/32 Pages) NXP

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NXP Semiconductors

SE050

Plug & Trust Secure Element

7 Pinning information

7.1 Pinning

7.1.1 Pinning HX2QFN20

aaa-031924

terminal 1

index area

Transparent top view

VOUT

ISO 7816 RST_N

ISO 7816 CLK

VIN

ENA

ISO 14443 LB

n.c.

ISO 7816 IO1

n.c.

SE050

Figure 4. Pin configuration for HX2QFN20 (SOT1969-1)

Note: Terminal 1 index area is marked on the bottom with a notch on the center pad and

on the top with a printed dot.

Symbol

Description

ISO 14443 LB

ISO14443 Antenna Connection, if not used connect to VSS

n.c.

not connected

ISO 7816 IO1

ISO 7816 IO or I2C controller SDA, if not used n.c (recommended) or connect

to VCC

n.c.

not connected

n.c.

not connected

n.c.

not connected

n.c.

not connected

n.c.

not connected

I2C_SDA

I2C target data, if not used n.c.

I2C_SCL

I2C target clock, if not used n.c.

ENA

Deep Power-down mode enable, if not used then connect to VCC

VIN

power supply voltage input for I2C pads and ISO 7816/14443 interface and

logic supply in case Deep Power-down mode is used

Table 5. Pin description HX2QFN20

SE050

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 3.5 — 22 August 2022

504935

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