ADP3192

Rev. 0 | Page 8 of 32

Pin No.

Mnemonic

Description

21

IMON

Analog Output. Represents the total load current.

22 to 25

SW4 to SW1

Current Balance Inputs. Inputs for measuring the current level in each phase. The SW pins of unused phases

should be left open.

26

NC

No Connection.

27 to 30

PWM4 to

PWM1

Logic-Level PWM Outputs. Each output is connected to the input of an external MOSFET driver such as the

ADP3120A. Connecting the PWM4, and PWM3 outputs to VCC causes that phase to turn off, allowing the

ADP3192 to operate as a 2-, 3-, or 4-phase controller.

31

VCC

Supply Voltage for the Device. A 340 Ω resistor should be placed between the 12 V system supply and the VCC

pin. The internal shunt regulator maintains VCC = 5 V.

32 to 39

VID7 to VID0

Voltage Identification DAC Inputs. These eight pins are pulled down to GND, providing a logic zero if left open. When

in normal operation mode, the DAC output programs the FB regulation voltage from 0.5 V to 1.6 V (see Table 4).

40

VIDSEL

VID DAC Selection Pin. The logic state of this pin determines whether the internal VID DAC decodes VID0 to VID7

as extended VR10 or VR11 inputs.