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EM6580 Datasheet(PDF) 21 Page - EM Microelectronic - MARIN SA |
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EM6580 Datasheet(HTML) 21 Page - EM Microelectronic - MARIN SA |
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21 / 56 page ![]() R EM6580 Copyright © 2006, EM Microelectronic-Marin SA 21 www.emmicroelectronic.com Output multiplexing registers are shown below. Table 6.4.7 Register RegPACntl3 Bit Name POR R/W Description 3 SerialStPA[3] 0 R/W Output selection for PA[3] when output 2 SerialCkPA[1] 0 R/W Output selection for PA[1] when output 1 PWMoutPA[1] 0 R/W Output selection for PA[1] when output 0 PWMoutPA[0] 0 R/W Output selection for PA[0] when output Table 6.4.8 Register RegPACntl4 Bit Name POR R/W Description 3 NoPdPA[5] 0 R/W No pull-down on PA[5] 2 freqOutPA[5] 0 R/W Output selection for PA[5] when output 1 Sout/rstPA[2] 1 R/W Output selection for PA[2] when output 0 freqOutPA[2] 1 R/W Output selection for PA[2] when output Table 6.4.9 PA[0] I/O status depending on its RegPACntl3 and RegPa0OE registers OEnPA[0] PWMoutPA[0] Description of PA[0] terminal 0 X Input 1 0 PAout[0] general Output 1 1 PWM Output from the 10-Bit Counter Table 6.4.10 PA[1] I/O status depending on its RegPACntl3 and RegPa0OE registers OEnPA[1] SerialCkPA[1] PWMoutPA[1] Description of PA[1] terminal 0 X X Input 1 0 0 PAout[1] general Output 1 0 1 PWM Output from the 10-Bit Counter 1 1 X Sclk (Serial interface clock output) Table 6.4.11 PA[2] I/O status depending on its RegPACntl4 and RegPa0OE registers OEnPA[2] Sout/rstPA[2] freqOutPA[2] Description of PA[2] terminal 0 X X Input 1 0 0 PAout[2] general Output 1 0 1 Freq. Output (CPUClk,SysClk, 2kHz, 1Hz) 1 1 0 Sout (Serial interface data output) 1 1 1 High level ‘1’ during Reset state output 8kHz frequency output while out of reset state Low level ‘0’ output during sleep 0 PA[0] = ‘1’ PA[4] = ‘1’ PA[1] = ‘0’ 1 1 Output: high level during Reset state Input: out of reset state and during sleep Frequency output is selected in 6.4.6 Register RegFreqRst Table 6.4.12 PA[3] I/O status depending on its RegPACntl3 and RegPa0OE registers OEnPA[3] SerialStPA[3] Description of PA[3] terminal 0 X Input 1 0 PAout[3] general Output 1 1 Rdy/CS (Serial interface status output) Table 6.4.13 PA[5] I/O status depending on its RegPACntl4 and RegPA1 registers OEnPA[5] freqOutPA[5] Description of PA[5] terminal 0 X Input 1 0 PAout[5] general Output 1 1 Freq. Output (CPUClk,SysClk, 2kHz, 1Hz) Frequency output is selected in 6.4.6 Register RegFreqRst Note: CPUClk = RCClk if no external clock used. In case of external clock, CPUClk is equal to the PA[1] input clock. |
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