EM6682 datasheet(28/61 Pages) EMMICRO

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EM6682

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The PWM signal generation is independent of the limited or full bit compare selection bit SelIntFull. However if SelIntFull = 1

(FULL) and the counter compare function is limited to lower than 10 bits one can generate a predefined number of output

pulses. In this case, the number of output pulses is defined by the value of the unused counter bits. It will count from the start

value until the IRQComp match.

One must not use a compare value of hex 0 in up count mode nor a value of hex 3FF (or FF,3F, F if limited bit compare) in

down count mode.

For instance, loading the counter in up count mode with hex 000 and the comparator with hex C52 which will be identified as

- bits[11:10] are limiting the counter to limits to 4 bits length, =03

(BitSel[1,0])

- bits

[9:4] are the unused counter bits = hex 05 (bin 000101),

(number of PWM pulses)

- bits

[3:0] (comparator value = 2).

(length of PWM pulse)

Thus after 5 PWM-pulses of 2 clocks cycles length the Counter generates an IRQComp and stops.

The same example with SelIntFull=0 (limited bit compare) will produce an unlimited number of PWM at a length of 2 clock

cycles.

8.4.1 How the PWM Generator works.

For Up Count Mode; Setting the counter in up count and PWM mode the PA[0] or PA[1] PWM output is defined to be 0

(EnComp=0 forces the PWM output to 0 in upcount mode, 1 in downcount). Each Roll Over will set the output to ‘1’ and each

Compare Match will set it back to ‘0’. The Compare Match for PWM always only works on the defined counter length. This,

independent of the SelIntFull setting which is valid only for the IRQ generation. Refer also to the compare setup in chapter

105H105H

In above example the PWM starts counting up on hex 0,

2 cycles later compare match

PWM to ‘0’,

14 cycles later roll over

PWM to ‘1’

2 cycles later compare match

PWM to ‘0’ , etc. until the completion of the 5 pulses.

The normal IRQ generation remains on during PWM output. If no IRQ’s are wanted, the corresponding masks need to be set.

In Down Count Mode everything is inverted. The

PWM output starts with the ‘1’ value. Each Roll Over will set the output to ‘0’ and each Compare Match will set it

back to ‘1’. Due to this, the positive pulse length is always longer by 1 selected clock period compared to written

value. Example: for 25% positive pulse duty cycle on 4 bit counter one must write 3 in counter if down-count

instead of value 4 in case of up-count.

Note:

In downcount mode and limited pulse generation one must load the complementary pulse number value. I.e. for

5 pulses counting on 4 bits load bits[9 :4] with hex 3A (bin 111010).

Figure 21. PWM Output in Up Count Mode

Data+2

Data+1

Data-1

Data

...

001

000

03F

03E

PWM output

IRQComp

IRQCount0

Compare

Roll-over

Count[9 :0]

Clock

Figure 22. PWM Output in Down Count Mode

Data-2

Data-1

Data+1

Data

...

3FE

3FF

000

001

PWM output

IRQComp

IRQCount0

Compare

Roll-over

Count[9 :0]

Clock

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