ADN2860 datasheet(4/20 Pages) AD

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ADN2860

Rev. A | Page 4 of 20

Parameter

Symbol

Conditions

Min

Typ1

Max

Unit

Input Leakage Current (Excluding WP

and A0)

VIN = 0 V or VDD

±1

µA

Input Capacitance5

POWER SUPPLIES

Single-Supply Power Range

VDD

VSS = 0 V

2.7

5.5

Dual-Supply Power Range

VDD/VSS

±2.25

±2.75

Positive Supply Current

IDD

VIH = VDD or VIL = GND, VSS = 0 V

µA

Negative Supply Current

ISS

VIH = VDD or VIL = GND, VDD =

2.5 V, VSS = −2.5 V

−5

−15

µA

EEMEM Data Storing Mode Current

IDD_STORE

VIH = VDD or VIL = GND

EEMEM Data Restoring Mode Current

IDD_RESTORE

VIH = VDD or VIL = GND

2.5

Power Dissipation7

PDISS

VIH = VDD = 5 V or VIL = GND

µW

Power Supply Sensitivity5

PSS

∆VDD = 5 V ± 10%

0.01

0.025

%/%

1 Typical represents average readings at 25°C, VDD = 5 V.

2 Resistor position nonlinearity error R-INL is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper

positions. R-DNL measures the relative step change from ideal between successive tap positions.

3 INL and DNL are measured at VW with the RDAC configured as a potentiometer divider similar to a voltage output D/A converter. VA = VDD and VB = 0 V.

4 Resistor Terminals A, B, and W have no limitations on polarity with respect to each other.

5 Guaranteed by design and not subject to production test.

6 Bandwidth, noise, and settling time are dependent on the terminal resistance value chosen. The lowest R value results in the fastest settling time and highest

bandwidth. The highest R value results in the minimum overall power consumption.

7 PDISS is calculated from (IDD × VDD). CMOS logic level inputs result in minimum power dissipation.

SDA

SCL

t10

Figure 2. I2C Timing Diagram

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