ADN2860 datasheet(17/20 Pages) AD

17 / 20 page

ADN2860

Rev. A | Page 17 of 20

POWER-UP SEQUENCE

Because the ESD protection diodes limit the voltage compliance

at the A, B, and W terminals (Figure 30), it is important to

power VDD/VSS before applying voltage to the A, B, and W

terminals. Otherwise, the diode is forward biased such that

VDD/VSS are powered unintentionally, which affects the rest of

the circuit. The ideal power-up sequence is as follows: GND,

VDD, VSS, digital inputs, and VA/B/W. The order of powering VA,

VB, VW, and the digital inputs is not important, as long as they

are powered after VDD/VSS.

LAYOUT AND POWER SUPPLY BIASING

It is always a good practice to use compact, minimum-lead-

length layout design. Make the leads to the input as direct as

possible with a minimum conductor length. Make sure that

ground paths have low resistance and low inductance.

It is also a good practice to bypass the power supplies with

quality capacitors. Use low equivalent series resistance (ESR)

1 µF to 10 µF tantalum or electrolytic capacitors at the supplies

to minimize any transient disturbance and filter low frequency

ripple. Figure 31 illustrates the basic supply-bypassing

configuration for the ADN2860.

VDD

VSS

VDD

VSS

GND

ADN2860

µF

0.1

µF

0.1

µF

Figure 31. Power Supply Bypassing

Solder the slug on the bottom of the LFCSP package to a floating

pad to improve thermal dissipation. Do not connect the slug to

a ground plane on the PCB.

RDAC STRUCTURE

The patent pending RDAC contains a string of equal resistor

segments with an array of analog switches. The switches

together act as the wiper connection.

The ADN2860 has two RDACs with 512 connection points,

allowing it to provide better than 0.2% progammability

resolution. The ADN2860 also contains a third RDAC with

128-step resolution.

Figure 32 shows an equivalent structure of the connections

between the two terminals that make up one channel of an

RDAC. The SWB switch is always on, while one of switches

SW(0) to SW(2N − 1) may or may not be on at any given time,

depending on the resistance position decoded from the data bits

in the RDAC register.

Since the switches are nonideal, there is a 100 Ω wiper resistance,

RW. Wiper resistance is a function of supply voltage and

temperature; lower supply voltages and higher temperatures

result in higher wiper resistances. Consideration of wiper

resistance dynamics is important in applications in which

accurate prediction of output resistance is required.

RDAC

WIPER

AND

DECODER

DIGITAL

CIRCUITRY

OMITTED FOR

CLARITY

RS = RAB/2N

SWB

SW(0)

SW(1)

SW(2N–1)

SW(2N–2)

SWA

Figure 32. Equivalent RDAC Structure

CALCULATING THE PROGRAMMABLE RESISTANCE

The nominal resistance of the RDAC between the A and B

terminals is available in 25 kΩ or 250 kΩ. The final two or three

digits of the part number determine the nominal resistance

value, for example, 25 kΩ = 25 and 250 kΩ = 250.

The following discussion describes the calculation of resistance

RWB(d) at different codes of a 25 kΩ part for RDAC0. The 9-bit

data-word in the RDAC latch is decoded to select one of the 512

possible settings.

The first wiper connection starts at the B terminal for data 0x000.

RWB(0) is 100 Ω of the wiper resistance and is independent of

the full-scale resistance. The second connection is the first tap

point where RWB(1) becomes 48.8 Ω + 100 = 148.8 Ω for data

0x001. The third connection is the next tap point representing

RWB(2) = 97.6 + 100 = 197.6 Ω for data 0x002, and so on. Each

LSB data-value increase moves the wiper up the resistor ladder

until the last tap point is reached at RWB(511) = 25,051 Ω. See

Figure 32 for a simplified diagram of the equivalent RDAC circuit.

These general equations determine the programmed output

resistance between terminals W and B.

ADN2860 Datasheet(PDF) 17 Page - Analog Devices

ADN2860 Datasheet(HTML) 17 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20

Datasheet Download

Link URL