ADN2860 datasheet(10/20 Pages) AD

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ADN2860

Rev. A | Page 10 of 20

INTERFACE DESCRIPTIONS

I2C INTERFACE

All control and access to both EEPROM memory and the RDAC

registers are conducted via a standard 2-wire I2C interface.

Figure 2 shows the timing characteristics of the I2C bus.

Figure 16 and Figure 17 illustrate standard transmit and receive

bus signals in the I2C interface.

These figures use the following legend:

From master to slave

From slave to master

S = Start condition

P = Stop condition

A = Acknowledge (SDA low)

A = Not acknowledge (SDA high)

R/W = Read enable at high and write enable at low

SLAVE ADDRESS

0 = WRITE

DATA

DATA TRANSFERRED

(N BYTES + ACKNOWLEDGE)

DATA

A/A

R/W

Figure 16. I2C—Master Transmitting Data to Slave

SLAVE ADDRESS

1 = WRITE

DATA

DATA TRANSFERRED

(N BYTES + ACKNOWLEDGE

DATA

R/W

Figure 17. I2C—Master Reading Data from Slave

SLAVE ADDRESS

READ OR WRITE

DATA

(N BYTES + ACKNOWLEDGE)

A/A

R/W

SLAVE ADDRESS

READ OR WRITE

REPEATED START

DATA

(N BYTES + ACKNOWLEDGE)

A/A

R/W

DIRECTION OF TRANSFER MAY

CHANGE AT THIS POINT

Figure 18. Combined Transmit/Read

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