AD9959

Preliminary Technical Data

Rev. PrB | Page 4 of 9

Maximum Clock Rise/Fall Time

TBD

ns

TBD

ns

Minimum Data Hold Time

TBD

ns

MISC TIMING CHARACTERISTICS

Master_Reset minimum Pulsewidth

TBD

Sync CLK

I/O_Update minimum Pulsewidth

1

Sync CLK

Minimum setup time (IO_Update to Sync_CLK)

TBD

ns

Rising edge to rising edge

Minimum hold time (IO_Update to Sync_CLK)

0

ns

Rising edge to rising edge

Minimum setup time (Profile inputs to Sync_CLK)

TBD

ns

Minimum hold time (Profile inputs to Sync_CLK)

0

ns

DATA LATENCY (PIPE LINE DELAY)

Pipeline delays for Freq, Phase,

Amp changes are programmable to

match one another.

Matched pipe line of Freq, Phase, Amplitude

TBD

Sys Clks

matched

Frequency word to DAC output

TBD

Sys Clks

unmatched

Phase Offset word to DAC output

TBD

Sys Clks

unmatched

Amplitude word to DAC output

TBD

Sys Clks

unmatched

CMOS LOGIC INPUTS

2.2

V

0.6

V

Logic 1 Current

3

12

uA

Logic 0 Current

-12

uA

Input Capacitance

2

pF

CMOS LOGIC OUTPUTS (1 mA Load)

2.8

V

0.4

V

POWER SUPPLY

Total Power Dissipation- all channels ON, single-tone mode

TBD

mW

Maximum Power Dissipation- all channels, freq accumulator

output multiplier ON

TBD

Iavdd – All Channels ON, Single tone mode

TBD

mA

Iavdd – All Ch(s) ON, Freq accum, and output multiplier ON

TBD

mA

Idvdd – All Ch(s) ON, Single tone mode

TBD

mA

Idvdd – All Ch(s) ON, Freq accum, and output multiplier ON

TBD

mA

Idvdd_I/O

TBD

mA

Power down Mode

TBD

mA