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AD9959 Datasheet(PDF) 6 Page - Analog Devices

Part # AD9959
Description  4 Channel 500MSPS DDS with 10-bit DACs
PDF  9 Pages
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Manufacturer  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

AD9959 Datasheet(HTML) 6 Page - Analog Devices

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AD9959
Preliminary Technical Data
Rev. PrB | Page 6 of 9
PRODUCT OVERVIEW
The AD9959 consists of four independently programmable
DDS channels. The AD9959 features independent frequency,
phase, and amplitude control of each channel; this allows for the
correction of imbalances due to analog processing such as
filtering, amplification, or PCB layout related mismatches. The
AD9959 supports frequency sweeping for radar and
instrumentation applications. Since all four channels share a
common system clock, they are inherently synchronized. If
more than four channels are required, synchronizing multiple
AD9959s is a simple task.
The AD9959 uses advanced DDS technology which provides
low power dissipation with high performance. The device
incorporates four integrated high speed 10-bit DACs with
excellent wideband and narrowband SFDR. Each DDS has a 32-
bit frequency tuning word, 14-bits of phase offset, and a 10-bit
output scale multiplier.
Each DAC has it own programmable reference to enable a
different full scale current for each channel.
Each DDS acts as a high resolution frequency divider with the REF_
CLK as the input and the DAC providing the output. The REF_CLK
input source is common to all DDS channels, and can be driven
directly, or used in combination with an integrated REF_CLK
multiplier (using a PLL) up to a maximum of 500 MSPS. The REF_
CLK multiplication factor is programmable from 4 to 20, in integer
steps. The REF_CLK input features an oscillator which supports either
a crystal as a source, or may be bypassed. The crystal frequency must
be between 20MHz and 30MHz. The crystal can be used with or
without the REF_CLK multiplier.
The DAC outputs are supply referenced and must be terminated into
AVDD by a resistor, or an AVDD center-tapped transformer.
The AD9959 comes in a space-saving 56-lead LFCSP package. The
DDS core (AVDD and DVDD pins) must be powered by a 1.8V supply.
The digital I/O interface (SPI) operates at 3.3V and requires that the
pin labeled “DVDD_I/O” (pin 49) be connected to 3.3V.
The AD9959 operates over the industrial temperature range of -40C to
+85



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